Oversampled Delta-Sigma Modulators: Analysis, Applications and Novel Topologies

If the error persists, contact the administrator by writing to support infona. You can change the active elements on the page buttons and links by pressing a combination of keys:. Polski English Login or register account. Abstract Oversampled Delta-Sigma Modulators: Assign yourself or invite other person as author. It allow to create list of users contirbution. Assignment does not change access privileges to resource content.

You're going to remove this assignment. University of Rochester, USA. University of Westminster, UK. Additional information Copyright owner: You have to log in to notify your friend by e-mail Login or register account. High contrast On Off. Change font size You can adjust the font size by pressing a combination of keys: Navigate the page without a mouse You can change the active elements on the page buttons and links by pressing a combination of keys: Noting that, by definition, the average output current is the PFD constant, K, , multiplied by the phase error ,.

Logic "I" "in - Reset. Phase-Frequency Detector 'aii, A very simple low-pass filter can be used in the charge-pump loop filter, which is made of a series connection of a capacitor C, and a resistor R see Figure 5. At the end of the charging interval, the current switches off and another voltage jump with negative sign cancels off the first abrupt change. Although the net effect is zero, this causes the VCO to be frequency modulated and is responsible for the generation of reference spurs recall that the comparison in the PFD is made approximately at the reference frequency [61], [78].

To suppress these undesirable spurs, a capacitor c, can be connected in parallel with the resistor. The capacitor c, has very little effect on the dynamics of the PLL, if it is chosen small compared to C, [13]. We will investigate this issue in further detail in Section 5. A Charge-pump loop filter I 5. An important criterion, in addition to high frequency agility and low cost 1 implementation, is the signal purity of the synthesized outputs in terms of phase noise Cjitter and spurious content [60]. One drawback of the traditional PLL frequency synthesizers described above, is that the output I frequency resolution is the same as the input reference frequency, thus imposing some compromises on the phase jitter perfonnance, frequency resolution and transient response of the synthesizer [61].

On the other hand, the switching or settling time of the synthesizer is determined by the inverse of the loop bandwidth [64]. Therefore, it is always desirable to use a small division ratio N with a large loop bandwidth [60], [61]. In these conditions, I the desired frequencies can only be achieved with a relatively high input frequency, which of course corrupts the output frequency resolution or the step size.

Thus, in order to provide small step sized moves between adjacent channels, a very low reference frequency is required. However, the use of a I very low reference frequency results in very high division ratio, which corrupts the phase noise perfonnance of the PLL [64].

• Item Preview?
• Unknown error!
• Post navigation.
• Pintura. Cuestiones y recursos (Spanish Edition);

Additionally, the PLL loop bandwidth must also be decreased in this condition resulting in long settling time [64]. The Fractional-N concept has been radically proposed to produce a step I size finer than the input reference frequency [62]-[64]. There is no frequency divider that can divide by a fractional number, but by making the division ratio in the feedback path to alternate between predetermined integer numbers in a controlled and repetitive fashion, a fractional number is obtained on the average sense. The advantages of this new system are obvious. First, for the same frequency resolution, a lower division ratio can be used.

This results in significant reduction in the overall phase noise performance of the PLL. Secondly, as the reference frequency is much higher compared to the frequency resolution, wider loop bandwidth can be used, which in turn reduces the settling time of the PLL. The duty-cycle for the accumulator carry bit is always K I F t i and F are integers , where K is the dc input binary word to the accumulator, and F is the accumulator size.

• Download Oversampled Delta Sigma Modulators Analysis Applications And Novel Topologies?
• Life Lessons: What I learned during my career in law enforcement… and in life.
• 26 décisions pour retrouver la forme (Santé, bien-être) (French Edition)!
• User assignment?
• INFONA - science communication portal.

In other words, the accumulator carry flag set to "1" K times in every F cycles. Note that there are exactly 3 accumulator carry outputs for each 16 I cycles. However, the first generation Fractional-N synthesis technique suffers from an abrupt change in the phase error, thus the process causes spurious signals that have to be attenuated by a lower loop bandwidth [62], [63]. While the divider is programmed to divide by ,v , the phase error begins to advance.

This periodic modification results in a saw-tooth phase error, which is responsible for the undesirable spurious generation [64]. The phase perturbation at the phase detector is entirely predictable and an analog compensation signal can be derived from the accumulator content to suppress the spurious components [60], [61]. This analog spurious I suppression technique, however, suffers from implementation imperfections because of a DIA converter required to convert the accumulator content into voltage.

The DIA converter puts more stringent requirements on the implementation while increasing the cost and power consumption of the overall synthesizer. Some other forms of suppression techniques were also developed in the art such as those based on phase interpolation and Wheatley random jittering [61]. Both of the methods have their own inherent disadvantages.

For example, the phase interpolation technique suffers from the phase jitter problem during the interpolation process, whereas in the Wheatley random jittering approach the resulting phase noise is nearly white. Consequently, this kind of suppression techniques are not suitable for wireless transceiver applications where low-cost and low-power implementations are important while still requiring low-phase-noise and spurious free performance [64].

As an alternative approach, oversampling noise shaping techniques have recently received a lot of attention for spurious suppression in Fractional-N synthesizers [62]-[64]. The basic idea of the noise shaping technique is to shape the spectrum of the quantization noise such that its power within the useful slgnal band becomes very much smaller. The idea of using a AX modulator to control the division ratio in a Fractional-N PLL comes from the fact that an accumulator is an equivalent digital implementation of the first-order AX modulator.

To see this, let us consider a first-order AX modulator with error-feedback topology as shown in Figure 5. The signal-flow graph for this modulator in its digital implementations is illustrated in Figure 5. The residual m -bit signal, which represents the negative of the quantization error signal, is then stored in an ni -bit register to be summed with the input signal at the next clock cycle.

The accumulator overflow and the accumulation result correspond to the single-bit quantizer output and the negative of the quantization error at any time, respectively, as suggested by the signal-flow graph in Figure 5. So an accumulator has the same first-order noise shaping property as the first-order AX modulator with error- feedback topology. First-order AX modulator with error-feedback topology: A fourth-order all-digital MASH modulator: This convention has been used to indicate that the input and output in Figure 5.

In Fractional-N frequency synthesis applications, the divider modulus control using a first-order AC modulator produces significant unwanted spurious components since lower-order modulators are prone to generating limit cycle oscillations and tones when driven by a constant input. As we have proven in Chapter 3 and Chapter 4, higher-order AC modulators both single-stage and multi-stage are capable of producing tone free outputs provided that the first accumulator is started with an irrational initial condition. Higher-order single-stage modulator, however, require that the amplitude of the input signal is limited to half of the quantizer bin width for no- overload stability, which in turn reduces the available tuning range in a Fractional-N frequency synthesis application.

Oversampled Delta-Sigma Modulators: Analysis, Applications and Novel Topologies | Analog Lib

MASH type modulators have, therefore, enjoyed a wide-spread usage in such applications [62], [64], and [80]. Using the fact mentioned earlier on, that a digital accumulator is the compact realization of a first-order AC modulator, the digital implementation of the fourth-order MASH of Figure 5.

The main disadvantage of MASH type modulators is that the quantization noise power at the output is related to that of the single-bit quantizer in the last stage. Although, the output is multi-bit in MASH modulators, this does not result in reduced quantization noise power, unlike multi-bit single-stage modulators. Our analysis will be based on an equivalent LTI system, which has the same average current flowing into or out of the loop filter as shown in Figure 5.

Referring to this figure, the voltage-to-average current transfer function for the low-pass loop filter can be given as follows ignoring c,: Assume that the loop begins with a phase error ,. The average change in the control voltage t', s can be found using 5. Since the discrete-time loop filter produces an output voltage vc [ n l , which is only known at certain time instants n T. To demonstrate the functional correctness of this complete model, we have performed various simulations. For example, Figure 5. The effect of this irrational initial condition in eliminating the spurious components is clearly obvious.

The only visible spurs are those of the reference frequency located at a 20 MHz distance from the synthesized frequency , whose power is 7 5 dB with the respect to the synthesized signal. In this case, the irrational initial condition provided an overall spurious free phase noise floor, which is 10 dB better than the uncompensated system.

This reduction in the phase noise floor comes from the fact that the energy contained in the discrete spurs are randomly distributed to the higher frequencies, where the low-pass loop filter can attenuate them.

User assignment

It should also be noted that the spurious free operation of the synthesizer achieved using the "1" LSB initial condition is very important. This is because if any discrete spur is not converted into a random phase noise, it can be combined with a strong signal from an adjacent channel allocated for another user, resulting in a significant amount of interference between message signals [60], [61]. Again the spurs are eliminated by using the "1" LSB initial condition. Therefore, the phase noise increases up to a certain point, and then it starts to decrease from where the attenuation provided by the closed loop transfer hnction of the PLL begins to dominate the amplification of the NTF of the modulator.

In this case, the "1" LSB initial condition is not necessary, but it should be incorporated in any Fractional-N design to ensure that the PLL output spectrum is spurious free for all input cases. In other words, the use of the "1" LSB initial condition does not result in any noticeable frequency deviations. Zoomed-in version of Figure 5.

As shown in these figures, the synthesizer attains lock in less than 10 micro-seconds meeting and surpassing our design specification. The quantization noise in higher-order MASH modulators increases very rapidly at higher frequencies, and the second-order loop filter can only provide limited suppression. If it is desired to further suppress the out-of-band phase noise in the PLL output, then a higher-order for instance a third-order charge-pump loop filter should be used, which in turn makes the PLL a fourth-order system [ While a third-order structure would be simpler, it, on the other hand, suffers from structured spectral components present in the output spectrum.

For a third-order modulator, increasing the dynamic range of the accumulators improves the tracking accuracy, but lessens the effect of the "1" LSB initial condition in whitening the quantization error sequence see Chapter 3. This trade-off becomes less sensitive for a fourth or higher-order modulator, where the number of bits of the accumulators at which the structured components begin to contaminate the output spectrum, is beyond the practical limits of the fixed-point implementations i.

In the actual implementation of the fourth-order MASH, the limited precision of the accumulators results in the loss of accuracy. Therefore, before proceeding to the implementation it was necessary to determine the dynamic range of the accumulators to furnish the desired accuracy for the Fractional-N synthesis. Several fixed-point simulations of the fourth-order MASH were performed through Simulink MATLABTM [83] employing our proprietary fixed-point libraries developed for Simulink, and it was observed that accumulators with bit dynamic range provided substantially good tracking on the desired mean value.

The bit-true model was thoroughly simulated to validate its conformance to the desired specifications. Each accumulator employs a pipelined bit adder and a bit register. It can be easily seen that there is a long delay chain between the accumulator overflow outputs, and therefore they appear at different time instances. To provide synchronization among the carry overflows, they are captured in 1-bit registers before being forwarded to the error cancellation network. The error cancellation network performs the specific function of canceling the quantization noise from the first three stages and produces a 4- bit wide output.

A bit adder could be easily realized by using 24 full-adder FA logic circuits connected in cascade. However, carry propagation between each FA may significantly reduce the operation speed of the overall design. For speed-up purposes, we have decided to use six cascaded 4-bit Carry-Look- Ahead CLA adders in the realization of bit adders, as indicated in Figure 5.

Passar bra ihop

Typically, a CLA adder circuit consists of three sub-systems, which are called the propagate generator, the carry generator and the sum generator. The logic equation for each sub-system is given below [84]: I,, c, and s, represent the i"' bit of the first input, second input.

Circuit realization of 1 - 1 - 1 -1 MASH The carry propagation between each CLA stage results in the critical delay path within the bit adder, and thus the maximum achievable operating frequency in a given process is limited by the overall computation speed of the six 4-bit CLA adders. A bit CLA would not suffer from the carry chain problem and may provide faster operation speeds. A simple approach to break the long carry chain in adders is to employ the pipelining technique so that the carry information is only forwarded by one stage [82].

The bits of both inputs of the adder should be appropriately delayed to synchronize them with the true carry signals. Conversely, the output bits are realigned in time by likewise employing the appropriate delays. Previously, it was reported in [85], that an accumulator is also pipelined in a similar way but without the need of time alignment registers for the second input, since it is taken from the delayed output of the accumulator.

I A three-bit example of such a pipelined accumulator is shown in Figure 5. Clearly, this topology operates on general time varying inputs. Since the AC modulator input is constant for the entire time, the input and output alignment registers can be completely eliminated in Fractional-N frequency synthesis applications. Consequently, a pipelined accumulator as shown in Figure 5. The error cancellation network basically performs the following knction [86]: Basically, there are three stages in the error cancellation network.

The first stage performs the following operation: This is accomplished by using a 4-bit two-input cany ripple adder and a simple logic as shown in Figure 5. It is clear from 5. The third stage is designed to perform one more addition with the C , to produce the final output. The logic incorporated in the error cancellation network takes four inputs and outputs two signals according to the following relation: Logic design o f error cancellation network The output of the MASH is a signed multi-bit 4-bit number, and two's complement binary number representation was chosen since it allows simple addition and subtraction.

The coding table of the MASH output indicating the output bits and their corresponding level is shown in Table 5. The reported maximum achievable operating frequency was 34 MHz this was 13 MHz before the pipelining was applied , which provides the desired clocking frequencies for the Fractional- N synthesis applications. These spectra were obtained by Hanning windowed 2'tpoint FFT data that was normalized to the single-bit quantization step size, which in our case was one. Furthermore, for 2'' samples of modulator output the fraction was represented to an accuracy of Output quantization noise spectrum of fourth-order MASH: We have seen that the PLL can be model as a linear system when it is in the lock condition.

A small-signal model was derived for a PLL from which the closed loop and open-loop transfer functions have been derived. The effect of the choice of the loop filter on the PLL dynamics has also been investigated. An active low-pass loop filter with a very large dc gain is required to achieve a relatively low static phase error [78]. The Op-amp within the active loop filter, however, introduces implementation challenges. A simple way for achieving low static phase error is the charge-pump technique [61], [78].

An overview of the Fractional-N synthesis technique was given. In random jittering techniques, the division ratio of the dual modulus divider is changed in a pseudo-random fashion. This technique, however, increases the phase noise floor of the synthesizer, because the injected phase jitter is nearly white [61]. The phase interpolation technique introduces frequency and phase jitter in the frequency divider [61]. As an ultimate solution, higher-order AC modulator controlled Fractional-N techniques were discussed. We have demonstrated that an accumulator is a compact realization of an all-digital first-order AC modulator with the error-feedback topology [79].

By using this, it was deduced that the first generation technique was actually a AC controlled Fractional-N synthesizer, where the order of the modulator was one. Better phase noise and spur performances can be achieved by using a higher-order modulator, instead of a first-order one [62], [63]. In this chapter, we have also developed a behavioral simulation model for the complete AX controlled Fractional-N PLL frequency synthesizers. The simulation model is especially very useful for accurately setting the PLL parameters prior to the real implementation. It is also very useful in assessing the spurious suppression performance of different AC modulator topologies in Fractional-N synthesis applications.

For instance, by using this simulator. To achieve the desired operation frequency range 20 MHz or higher while providing low-power dissipation and small area, the pipelining technique was utilized in the design, where the input and output alignment registers were eliminated by taking advantage of the constant nature of modulator input. In this approach, the time-domain expressions of a standard modulator are rearranged according to the desired channel count to produce a modular structure with reduced hardware requirements.

It is shown that the proposed approach results in an architecture, which is functionally equivalent to that of the existing method based on the block digital filtering concept, but with a reduced hardware complexity. The theoretical results are verified by means of behavioral simulations. We start our development with the modulators formed out of the cascaded integrators with distributed feedback topology. We then extend our method to cover a more advanced sub-class of modulators containing cascaded integrators with weighted feed-forward summation and cascaded integrators with distributed feedback as well as feed-forward branch topologies.

A new time-interleaving concept based on zero-insertion interpolation is also proposed, which eliminates the high sampling rate multiplexer at the input stage. In this scheme, the input signal is sampled at the operation frequency of the channels and applied only to the first channel whereas all other channels are fed with zeros all the time. In addition to their reduced hardware complexity and inherent high linearity, they also benefit from being robust against implementation imperfections such as circuit element inaccuracies [14].

A major shortcoming of AC modulators, however, is the limitation in their applications to relatively narrow bandwidth signals due to the oversampling requirement [5]-[7]. Several parallel AC approaches have been proposed to date offering the potential of extension to high-resolution oversampling noise shaping conversion for signals with higher bandwidths. The parallel approaches can be classified into three main categories.

A set of digital band-pass filters then attenuate the out-of-band noise at each channel allowing reconstruction of the frequency decomposed input signal. This scheme however, may not be practical in terms of hardware complexity, since band-pass AC modulators and band-pass filters are required for each channel having different center frequencies [88]. In this approach, referred to as n A C converter, the input signal is multiplied with a Hadamard sequence at each channel and quantized using standard low-pass AX modulators. The output of each modulator is filtered using low-pass filters, multiplied with the delayed version of the Hadamard sequence and finally added together for re-composition [90].

A significant advantage of this method is that it includes identical standard low-pass AC modulation at each channel. In this approach, the input is sampled at a high sampling rate and then distributed through a multiplexer over different channels, each operating at a slower rate. However, straightforward application of this approach results in only a small increase in SNR performance of the AC modulators [94]. Due to the recursive nature of these converters it was difficult to formulate the equivalent TI structure for a given modulator till the mid 90's.

Fortunately, in Poorfard et. This approach makes use of M mutually cross- coupled AX modulators each operating at a sampling rate of f , resulting in an effective sampling rate of Mf? In this chapter, a new design methodology utilizing the time-interleaving concept in noise shaping oversampled converters is explored and described.

In this approach, the time-domain internal node expressions of standard modulators are rearranged according to the desired channel counts, to produce efficient hardware architectures with modular structures and reduced hardware element counts. The TI counterparts of single-stage modulators containing Cascaded Integrators with a Distributed Feedback CI-DF topology are presented along with comparisons to those obtained using block digital filtering. It was shown that our novel approach resulted in fiinctionally equivalent structures as to those derived from the block digital filtering start-point, but with a considerable reduction in the hardware complexity.

We then extend this approach to a sub-class of modulators, which provide more suitable structures for higher-order oversampled noise shaping conversion. In fact, the primary focus of this chapter is the investigation of a new TI conversion technique based on the zero-insertion interpolation technique. In this new approach, the input is sampled at the operating frequency of the channels, and applied only to the first channel while all other channels are fed with zeros at all time. The readily available low-pass filter at the output of the AC modulator serves two purposes; i it rejects the spectral replicas of the input signal arising form the up-sampling, and ii it attenuates the out-of-band quantization noise.

In the next section, the block digital filtering approach as applied to the AC modulators is briefly discussed to provide the further details of this technique. The effect of mismatches between the inter-channel scaling coefficients is also investigated in this section. Verification of this approach is accomplished through examples on single-stage modulators with CI-DF topology for a variety of modulator order L and interleaving number M.

Finally, we provide some concluding remarks in Section 6. To set the scene, in this section we briefly discuss the basics of this approach.

Download Oversampled Delta Sigma Modulators Analysis Applications And Novel Topologies

The equivalent block filtering structure for a given single-input single- output SISO feed forward loop filter H Z is presented in Figure 6. This condition is necessary and sufficient for a block digital filter to represent a SISO linear-time-invariant transfer function [95]. H z integrator i Equivalent time-interleaved structure of a basic modulator obtained using block digital filtering. Although the block filter reveals that three additional delay elements are needed for realization, one simplification, we have made here is to take the first cross-connection from the delayed version of u , [n] instead of taking it directly from z i , [ t 7 ] see Figure 6.

Therefore, with the exception of the input multiplexer and output demultiplexer, in addition to two explicit integrators, two quantizers, two two-input subtractors and two DAC's, it also needs at least two delay elements, two two-input adders and two cross-connections between the channels. By performing linear analysis on the structure shown in Figure 6. TI first-order A 1 modulators derived using the block digital filtering approach: In this case, with the exception of the input multiplexer and output demultiplexer, four explicit integrators, four quantizers, four two-input subtractors and four DAC's, as well as at least four delay elements, twelve two-input adders and twelve cross-connections between channels are needed.

The input-output transfer function can be obtained as: We present all details with examples for our approach to achieve efficient architectures for time-interleaved oversampling converters. Our approach includes the following steps: The resulting time-interleaved AC converter architectures from our novel approach are modular and result in reduced hardware element counts [97]. Consider again the first-order modulator shown in Figure 6. Similarly, for the next time slot: Thus, we shall label the inputs as: Y, [n] - 1' [n] 6. The input multiplexer and output demultiplexer are the same in both structures, however the internal blocks are different.

In comparing the two structures it is convenient to quantify only the hardware required by each parallel channel. By carefully examining Figure 6. The proposed converter produces the same transfer function as that of the structure in Figure 6. To show this, we once again examine our proposed structure in the time domain as follows: The input-output transfer hnction for the proposed structure shown in Figure 6.

In the first application presented so far, the proposed method decreases the number of analog delay elements at the expense of a small increase in the number of cross-connections between channels, when compared to the block digital filtering approach. The increase in the required hardware by the block digital filtering approach is proportional to the square of the channel count M , whereas the hardware complexity of the proposed architecture is linearly related to the channel count [98].

The proposed scheme does solely necessitate four quantizers, four two-input subtractors, four DAC's, one delay element, four two-input adders and eight cross-connections between channels. Greater savings through our simplifications are now more evident as the interleaving number M increases.

The transfer function of the proposed four-channel time interleaved first- order modulator can be found from the following set of equations: To demonstrate that our proposed method is also applicable for any higher-order AX modulator as well, the two-channel time-interleaved versions of a second-order modulator as shown in Figure 6. The resultant architectures of both the block digital filtering and our proposed approaches are presented in Figure 6. Referring to Figure 6. Conversely, our proposed architecture needs two quantizers, four two-input substractors, two DAC's, two delay elements, four two-input adders and six cross-connections between channels see Figure 6.

However, such modulators can be made conditionally stable by using the appropriate scaling factors in the feedback loops. A third-order AZ modulator is shown in Figure 6. TI first-order AX modulators derived using our proposed approach: Using our proposed approach, the two-channel time-interleaved version of this-third-order AX modulator has been derived which is demonstrated in Figure 6. It should also be noted that the proposed architectures could be derived in the frequency domain utilizing the general block digital filtering theory too [97].

For the block digital filter implementation of 6. However, the proposed method may not necessarily result in simpler structures when the cross- coupling term is reduced from its nominal value of unity. Reducing the cross-coupling term is effective in alleviating the undesirable effects of some circuit imperfections in analog implementations [95]. To validate our theoretical results, simulations were carried out for these struchires. Throughout the simulations, all modulators were excited by a single tone sinusoidal signal at a frequency of 8 KHz with amplitude of 0.

It should also be noted that. Therefore, to provide the same resolution per bin in the frequency domain, the length of each periodogram was set to 32K for the standard modulator, whereas periodograms of K length were necessary for the four-channel time-interleaved modulators. To prevent limit cycle oscillations, the same amount of dithering was applied to each quantizer [5]-[7].

The output spectra for the standard and time-interleaved by four first- order modulators are shown in Figure 6. These spectra were generated using the Welch's spectrum estimation method, where a Hanning window has been applied throughout. The tall peak at 8 Id-Iz is of course the desired sinusoid, where the remaining components are the shaped quantization noise. The results in Figure 6. It is well known in the art that for a first-order modulator every doubling of oversampling ratio OSR corresponds to a 9 dB improvement in SNR performance [5].

A as a result, the four-channel time-interleaved first-order modulators as shown in Figure 6. Output spectra for standard and four-channel first-order AX modulators 6. Some of the practical limitations considered in this chapter are; finite Op-amp gain, Op- amp dc offsets, mismatch effects and sampling clock jitter. These are briefly discussed in the following subsection. As a result, the TI modulators are more robust against leaky integrators. This is because of the cross-terms taken from the adders' outputs.

Hence, the effect of the finite gain of the Op-amps is similar to the mismatch effect between branches, as aliasing occurs due to the discrepancy in the coefficients of the B: In these simulations, the standard modulator was clocked at twice the rate of the internal clock frequency of the TI modulators so that the noise floor is the same in all structures if A was assumed to be infinite.

On the other hand, in our proposed TI modulator the noise floor is marginally increased when compared to the standard modulator for the same finite values of A due to the aforementioned aliasing effect. As a result, our proposed structures are slightly less robust against the finite Op-amp gain non-ideality and may require the use of Op-amps with higher dc gains. Fortunately, there is a method to alleviate the effect of dc offset to some extent in this kind of TI modulators [95]. By reducing the cross-coupling coefficient k from its nominal value of unity l , the degree of overloading in quantizer inputs can be substantially reduced.

Hence, the block digital filtering TI modulators can be made robust to this non-ideality, provided that k is carefully chosen. On the other hand, in our proposed TI structures the dc offsets of Op- amps do not cause any probletns as the quantizer input at the first and second channel is fed back to the second and first channel, respectively, thereby essentially canceling the dc offsets in the respective branches. Our proposed TI modulators, therefore, have the capability of inherent overload protection at the quantizer inputs in a similar manner to what happens in standard modulators.

The two-channel TI first-order tnodulators of Figure 6. Actually, the quantizer inputs for the TI modulator of Figure 6. As shown in Fig. Output spectra for second-order modulators built out of leaky integrators: In [99], it was shown that due to mismatches, the block digital filtering implementation becomes time varying.. As discussed in the previous section, the k-factor method was not employed in our proposed structures. To overcome this problem, a two rank SIH structure can be used, in which the input signal is held constant by the first SIH device and then distributed to each channel by M SIH devices each operating with 2rr!

The same statement seems also to be true for our proposed TI modulators. In fact, both of the TI modulators need the usage of the clock staggering strategy in the analog implementation or pipelining techniques in the digital implementation to h l ly benefit from the parallel processing propriety offered by the approaches. A first-order AC modulator with error-feedback topology is shown in Figure 6. Its two-channel TI version derived using the proposed method is also given in panel b of this figure. The critical delay path is defined as the signal path, which includes no delay elements. The block diagram of Figure 6.

In digital implementations, however, the single-bit quantization and single-bit subtractor are embedded in the overilow mechanism of the multi-bit adder see Figure 5. In reality, the critical delay would be determined by the computation speed of one multi-bit adder accumulator. In the case of the time- interleaved modulator, the critical delay is determined by the total computation delay of two multi-bit adders. Obviously, the required computation speed is doubled in the time-interleaved case, which contradicts with the aim of the parallelism.

A simple solution to this is to utilize pipelined adders in the implementation. First-order AE tnodulators with error feedback topology: Since each carry information is stored in a register, one adder can start its calculation as soon as the LSB of the result from the other adder is ready1'. In this case, the critical delay path is determined by the time each full-adder unit in the adders needs to complete its calculation. Assuming that both of the standard and two-channel TI modulators are implemented using pipelined adders, we may conclude that the critical delay path would be the same in both architectures.

Therefore, with appropriate exploitation of pipelining technique the TI modulator can fully benefit from its parallel operation to increase the effective oversampling ratio. However, the same reasoning can be extended to the cany-save adders or carry-lookahead logic adders. In contrast, our proposed stnicture uses M L t I cross-connections between channels, L delay elements and LM two-input adders. Comparison of the block digital filtering and our proposed approaches in terms of hardware requirements Block digital filtering Proposed method Input multiplexer needed needed Output demultiplexer needed needed of quantizer A 4 A4 t oftwo-input subtractor L A4 LM of DAC'S M.

They are also less prone to generating idle tones and limit cycles. A major obstacle, however, is the stability issue, especially when a single-bit quantizcr is used. Oversampling noise shaping functions of order higher than two consisting of pure differentiation result in inherently unstable systems [7] with a single-bit quantizer. Consequently, higher- order single-stage modulators are realized by making use of some feedback scaling factors, which reduces the dynamic range of the modulator.

In this section, we extend our TI approach to a more general class of single-stage modulators by covering two different topologies as suggested by Adams in [38]: Derivation of the TI structure: Assuming that the DAC in the feedback loop is ideal i. Assume that the input x[n] is being distributed over two channels through an input multiplexer operating at twice the rate of the internal clock frequency of each channel.

Thus, we shall label the inputs of each channel as follows: The time-domain behavior of the two-channel TI counterpart can be found by combining equations 6. The desired TI modulator can be easily formed from equation 6. It is worth noting that the outlined procedure has resulted in a structure where there is no explicitly visible integration block. The accumulation process is, however, accomplished through the cross-connections between channels and the add-and-delay circuitry embedded on the second channel. Consequently and as expected, the TI modulator produces the same transfer function as that of the standard modulator.

By systematically applying the method outlined here for different modulator order L and interleaving number M , one can come up with generalized TI structures with an arbitrary interleaving number M as it comprises repetitive structures. Again by performing linear analysis, the transfer function of the M-channel TI modulator of Figure 6.

• 101 Margaritas.
• Unknown error!
• The DoomsDay Slayers;
• The Ultimate Erotic Short Story Collection 11: 11 Steamingly Hot Erotica Books For Women.
• Account Options;
• Nach uns die Kernschmelze: Hybris im atomaren Zeitalter (German Edition)?

Note that this linear analysis was aided with the use of the Matlab symbolic equation handling tool []. Throughout the simulations, a single tone sinusoidal excitation signal at a frequency of 8 KHz with an amplitude of 0. For the four-channel interleaved modulators, the effective sampling rate j , c,, is four times the modulator clock frequency f. Output spectra for higher-order AZ modulators standard vs.

The simulation results in Figure 6. Its four-channel TI counterpart produces an in-band SNR, which is approximately 54 dB better than that of the standard modulator operating at the same clock frequency. The simulation results presented in Figure 6. It is well kwon in the art that higher-order AX modulators are advantageous especially when a high OSR is used [7], [38]. The simulation results presented here indicate that there is only approximately 3.

However, when the effective sampling rate is increased by four through interleaving i. Generally speaking, any TI modulator is a multi-rate system and its successful operation relies on perfect aliasing cancellation [99]. In other words, the aliased components generated due to the down-samplers will be completely canceled in the final output if the system is ideal. In the CI-FFS topology, the quantizer input at each channel is obtained by multiplying the respective adder outputs with scaling coefficients and summing them.

Therefore a small deviation in the scaling factors among the channels does not pose any problem, as the sign of the quantizer inputs remains intact. Hence, we conclude that this topology is robust against this kind of mismatches when a single-bit quantizer is used. Fortunately, there is a way to reduce the amount of aliased noise in the baseband to a great extent. This can be easily accomplished by introducing notches in the NTF of the modulator at 2mlhf.

Our method, however, results in the same structure as the block digital filtering approach proposed by Poorfard et. The in-band SNR performance is improved by 11 dB compared to our proposed structure with mismatches. These notches increase the overall noise floor of the modulator, as the total power is constant at the output [95]. For instance, Figure 6. The resulting TI modulators do not employ any explicit integration blocks. All the accumulation processes are achieved at the Adh channel through the use of L add-and-delay elements. All other channels consist of only summation blocks, and therefore simplify processing requirements.

Rather than utilizing M cross-coupled AX modulator in parallel, our method suggests a way to share the already existing resources, and successfully reduces the complexity of the whole implementation. Although the resultant TI modulators are already efficient in terms of hardware complexity, the elimination of the high sampling rate input multiplexer would be advantageous.

In an effort to reduce the hardware complexity involved in the implementation of the high sampling rate input multiplexer, we have explored in this section a new TI concept based on our novel application of the zero-insertion interpolation technique. The underlying idea here, is that the input signal is sampled at the operating frequency of the individual channels f, of course, provided that f , respects the Nyquist criterion , and applied only to the first channel whereas the remaining channels are being fed with zeros at all time.

The output spectrum consists of the shaped quantization noise and the original input signal along with its spectral replicas arising from the up- sampling. The low-pass filter at the output of the AC modulator suppresses the high frequency quantization noise as well as the spectral replicas of the up-sampled input. Input signal distribution for interleaving approaches: A gain factor of M is incorporated, which scales the input signal, to compensate the input signal power loss at the output of the Z1-TI modulator due to the up-sampling, and will be explained in greater detail in the following paragraphs.

As can be seen from this figure, the major difference between the spectral characteristics of ZI-TI and regular TI scheme is the presence of the input signal replicas spaced at ,f, intervals, which were generated as a result of the zero-insertion up-sampling. However, these replicas are well below the modulator shaped quantization noise characteristic and lie outside the base-band region of the modulator.

A standard first-order modulator and its two-channel TI version, which was derived using the method outlined in Section 6. The transfer function of the TI modulator of Figure 6. Let us assume that there is a unity gain factor at the input. With this assumption, the transfer function for the ZI-TI modulator can be easily derived as: The analytically derived expressions given in 6.

IX f l 4 quantization noise Figure To eliminate this power loss due to zero-insertion up-sampling of the input signal, a gain factor of M is included at the input stage of the ZI-TI modulator. At a first glance, this gain factor may be deemed to be causing overloads at the quantizer inputs. However, a close investigation reveals that the internal nodes of the TI and TI modulators have nearly identical statistical characteristics such as mean, variance and maximum values.

Therefore the ZI-TI approach with input gain factor would conveniently utilize the same Op-amp characteristic in terms of signal swings as the regular TI structures []. Regarding the ZI-TI concept, the work we have reported so far has been backed by theoretical analysis for the first-order modulator. Due to the considerable complexity involved in the algebra of higher-order TI modulators with an interleaving number M greater than 2, we have opted to deploy the same input gain factor principle for the M path ZI-TI modulators as was suggested by the analytical first order results, without resorting to cumbersome algebra.

The TI versions of these modulators can be easily reconstructed from their corresponding ZI-TI structures by replacing the input gain factor with a high speed input multiplexer, and therefore not shown here. Simulations of these structures were carried out with the simulation parameters as was used for the four-channel higher-order modulators reported in Section 6. The results presented in Figure 6. Output spectra for second-order AX modulators: Both the standard and four-channel ZI-TI modulators were simulated with different input amplitudes up to 0.

This analysis can be easily extended to TI AZ modulators to derive a formula for the total jitter error power, with the simple inclusion of the oversampling factor. In an M-channel TI modulator the total jitter error power at the output can be expressed as [92], []: To illustrate the SNR degradation due to sampling clock jitter, the second-order modulator shown in Figure 6.

Here, the sampling rate of the standard modulator and hence the operation speed of the channels in the TI structure was set to 2. The input here was again an 8 KHz single tone sinusoidal signal. The second-order modulators were simulated for different input amplitudes and the result of this experiment is displayed in Figure 6. Simulated in-band SNR performances of second-order modulators under ideal and sampling clock jitter error conditions: The maximum in-band SNR is decreased by approximately 6.

The sensitivity to sampling clock jitter error is surprisingly increased for the ZI-TI approach. Even though, there is only one component that contributes to jitter error for the ZI-TI modulator, the gain factor of M at the input stage increases the jitter power by a factor M'. These results indicate that the two-channel ZI-TI second-order modulator is marginally more sensitive than the TI modulator as expected and suggested by equations 6. This is because of the fact that the in-band quantization noise power is substantially increased in comparison to the increase of the jitter error power.

In [95], branch mismatches were investigated thoroughly and the k-factor method was introduced to alleviate the effects of this problem. The two-channel second-order block digital filter TI Figure 6. In both of the regular TI and ZI-TI block digital filter structures, the k-factor method is very effective in correcting the aliased noise floor.

Unfortunately, the k-factor method is not applicable in our proposed modulators with their reduced complexity as discussed in Section 6. Hence, we have concluded that, while the proposed modulators have simpler hardware, they are less robust against branch mismatches when compared to the cited block digital filtering idea. Our proposed architectures result in modular structures and provide considerable reduction in the hardware requirements. The approach proposed here does not bring any restriction on the type of the modulator. However, it may not necessarily give simpler structures than the already existing approach based on the block digital filtering, for all cases i.

Theoretical analysis and simulation results have shown that our proposed TI modulators produce the same transfer functions as those of the block digital filtering approach.