Cache Canon

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AmazonGlobal Ship Orders Internationally. Amazon Inspire Digital Educational Resources. The advantage of such assignment will be described later. The arrangement of the data processing apparatus will be described below with reference to FIG. In the data processing apparatus , both the first and second pipelines and include eight stages. Judge[ 0 ] to Judge[ 7 ] correspond to the data processing circuits and shown in FIG.

As described above, by providing a plurality of stages, the data processing apparatus can distribute in parallel and compare many data elements by pipeline operations. The storage address is shifted by the Data Slots of the first pipeline of the data processing apparatus A cache apparatus using an example of the data processing apparatus corresponds to an 8-node, fully-associative cache apparatus.

The cache determination unit always discards cache tag and cache data in turn from the oldest ones although it has a very simple structure. As a result, complicated replace control of a general cache mechanism need not be executed. The cache hit determination sequence will be described below. When the designated data is stored in the cache memory , a cache hit is determined; otherwise, a cache miss is determined. The cache hit determination is made by the cache determination apparatus As a result, the cache hit determination can be attained by determining the sign of the data processing result in the last stage of the first pipeline Therefore, the cache determination can be done very simply.

For the mechanism which always discards cache data in turn from oldest cache data, as described above, the cache memory can use a ring type FIFO. In this case, the cache determination unit and cache memory can be easily synchronized. With the aforementioned processing, the cache determination unit outputs, to the access arbitration unit , as a determination result based on the input storage address The operation of the access arbitration unit will be described below with reference to FIG.

The operation of a cache memory arbitration unit will be described below. The cache memory arbitration unit evaluates whether or not data are held in the storage areas of the receiving queue and waiting queue When the waiting queue is empty, since there is no cache determination result to be processed, the cache memory arbitration unit waits without any processing.

The cache memory arbitration unit confirms if data which is not stored in the cache memory is received from the DRAM in the receiving queue If no data is received, the cache memory arbitration unit waits until data is received. If data is received, the cache memory arbitration unit dequeues cache data to be updated from the receiving queue Next, the cache memory arbitration unit increments the write pointer of the cache memory When the FIFO capacity is exceeded, the cache memory arbitration unit resets the write pointer to zero.

The cache apparatus distributes cache data obtained by the aforementioned process to the processing apparatuses to The cache apparatus includes a ring bus used to distribute cache data. The cache apparatus adopts a non-blocking cache mechanism so as to hide refill latency as a penalty at the time of a cache miss.

Then, the cache apparatus executes cache determination processing of the next pixel before completion of processing for reading out cache-missed data from the DRAM , and storing it in the cache memory With this processing, the cache apparatus can execute the cache determination for the subsequent pixel even while the cache-missed data is refilled from the DRAM to the cache memory Therefore, a performance degradation at the time of a cache miss can be suppressed.

The cache apparatus can implement a fully-associative cache apparatus, which can be shared by a plurality of processing apparatuses, using a very simple mechanism. When the plurality of processing apparatuses share one cache apparatus , addresses having low correlations are successively input to the cache determination unit Since a cache determination unit which adopts a general direct mapping method calculates a storage address of a tag memory used to manage a cache tag from lower bits of each address, a cache conflict is readily caused by such addresses having low correlations.

To increase the number of set-associative nodes in correspondence with the number of processing apparatuses is one solution to reduce the cache conflict probability. However, when the number of processing apparatuses becomes very large, a very large number of nodes have to be coped with. Hence, it becomes difficult for a general cache apparatus implementation method to converge timings since the number of logical stages of a selector in a cache determination unit is large, and that cache determination unit cannot be operated at a high operation frequency.

By contrast, since the cache determination unit attains determination by the pipeline configuration, it can operate at a very high operation frequency. Also, the cache determination unit does not require any complicated replace control at the time of a cache conflict, which is required in the related art, since data are automatically deleted in turn from older data. For this reason, the cache determination unit and cache memory arbitration unit can be synchronized by a very simple mechanism, and a FIFO can be used as the cache memory.

Hence, such arrangement is advantageous to improve the operation frequency of the cache apparatus More importantly, the cache apparatus adopts the fully-associative method, and never causes a cache conflict due to the same lower bits of addresses.

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A cache apparatus using a cache determination unit shown in FIG. The cache determination unit is used in place of the cache determination unit of the cache apparatus shown in FIG. A description of the same parts as in the basic arrangement of the aforementioned cache apparatus will not be repeated. The cache determination unit includes a replicating apparatus , operation apparatus , and cache determination apparatus The operation apparatus includes a plurality of data processing apparatuses D.

In this manner, since the cache determination unit includes the plurality of data processing apparatuses described above, the number of data elements which can be compared at the same time is increased.

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Since the cache determination unit shown in FIG. Respective Data Slots included in the cache determination unit are the same as the nodes and shown in FIG. In this way, replicas of the same storage address are input in parallel to the first pipelines of the respective data processing apparatuses at the same timing. Then, the node outputs data elements stored by itself to the access arbitration unit as the determination result As described above, in the cache apparatus using the cache determination unit shown in FIG.

Then, a fully-associative cache apparatus having a larger number of nodes can be easily implemented.

The cache apparatus using the cache determination unit includes a plurality of data processing apparatuses each having the basic arrangement, and can be implemented by connecting only the first pipelines and second pipelines of the respective data processing apparatuses. For this reason, a data processing apparatus which has already been designed and verified can be re-used. Also, the cache determination unit executes data processing using the pipeline configuration, and can determine a cache miss by calculating only logical products of all sign bits.

In this manner, the cache apparatus can operate at a very higher operation frequency than the conventional cache apparatus. Using these data elements, a write-back cache apparatus can be implemented.

In the write-back cache apparatus, cache data temporarily stored in the cache memory is replaced by write data written out by the processing apparatuses A to D For this reason, the data temporarily stored in the cache memory has to be saved in the DRAM as an external memory. In order to cope with the write-back cache apparatus and to allow the processing apparatuses A to D to perform write operations, the storage address to be output includes: The node outputs the determination result including these data to the access arbitration unit That is, this determination result includes: The determination result arrives the cache memory arbitration unit via the waiting queue Therefore, the cache memory arbitration unit need not save cache data temporarily stored at the storage address of the cache memory With the aforementioned arrangement, the write-back cache apparatus can be easily implemented.

The cache determination unit of the cache apparatus used as the write-back cache apparatus also has the same advantages as those of the read cache apparatus. Especially, data are automatically deleted in turn from older data, and complicated replace control at the time of a cache conflict need not be executed. Then, cache data temporarily stored in the cache memory need only be saved in turn from older data in the DRAM as an external memory.

As described above, write-back control unique to the write-back cache apparatus can be implemented by a very simple method. In this way, as in the cache determination unit , the cache determination unit includes the plurality of data processing apparatuses described above, thereby increasing the number of data elements which can be compared at the same time.

Furthermore, when the plurality of processing apparatuses A to D share the cache apparatus , the cache determination unit can switch a cache capacity the number of nodes to be exclusively used by each processing apparatus for respective processing apparatuses. By switching an exclusive assignment for each processing apparatus, a larger cache capacity the number of nodes can be assigned to image processing with a high priority level.

That is, upon execution of image processing, the exclusive assignment of a cache capacity the number of nodes is adaptively switched according to the purpose of image processing, thus executing the image processing with a desired efficiency. The replicating apparatus shown in FIG. Therefore, a description of parts common to those in the replicating apparatus will not be given, and the partition information table will be described below. In the partition information table , the CPU sets partition information in advance so as to switch assignments of cache capacities the numbers of nodes to be exclusively used by respective processing apparatuses.

The partition information table will be described in detail below with reference to FIGS.