Microwave Circuits for 24 GHz Automotive Radar in Silicon-based Technologies

The angle of arrival is then easily obtained by rearranging equation 2. Therefore, the spatial sampling theorem has to be fulfilled and the antenna separation has to be half-wavelength. For mid-range and long-range systems the spacing has to be chosen according to the beamwidth of the transmitter antenna. An increased spacing between the receiver antennas allows to increase the size of the antennas and thus the gain. Furthermore, this results in a direct improvement of the angle measurement accuracy. However, this results in an increased radar module size.

The maximum allowable power limits and 2. The limit for the transmitted power is given as equivalent isotropic radiated power EIRP. For the ultra-wide band from This spectral density is very low and can only be used by pulsed systems with high bandwidth. The ISM band of MHz is applicable for automotive mid-range to long-range applications, since these are typically implemented as continuous wave CW systems and require higher power to achieve the necessary maximum range.

CW systems provide a higher SNR compared to pulsed systems for the same transmitter power. Furthermore, the narrow available bandwidth of the ISM band is practical, since the maximum bandwidth is limited by the required signal to noise ratio at the maximum range [2]. Apart from the automotive radar systems, the ISM band is used for less demanding applications, such as door openers or surveillance. These systems are implemented using Doppler sensors without any additional frequency modulation. Therefore, the requirements for the receiver performance are usually very demanding. It should offer low noise, high dynamic range, and high local oscillator LO isolation so as to avoid radiation emission.

The choice of receiver architecture is usually determined by complexity, power dissipation and system considerations. Receiver architectures can be classified with respect to the down-conversion topology. The frequency of the local oscillator LO is equal to the carrier frequency of the received RF signal. This architecture offers the advantage of simplicity. Avoiding an additional down-conversion to an intermediate frequency IF saves chip area, current consumption, complexity and avoids the image rejection problem inherent to heterodyne systems. A simplistic block diagram of a continuouswave radar system implementing a homodyne receiver is presented in Fig.

The spectrum diagram of a homodyne receiver is depicted in Fig. Both upper and lower side bands are down-converted to zero-IF. However, it has a serious disadvantage when implemented in CMOS technology. Thus, for an active mixer implementation very high noise figures of above 40 dB at 1 kHz can occur. Therefore, either implementation of advanced circuit techniques [9] or of passive mixers [10] is required to resolve this issue. This problem will be addressed in detail in chapter 6. Bipolar transistors have a 2. However, there is an additional disadvantage.

The DC offset can be suppressed by DC blocking capacitors. The high-pass characteristics offered by these capacitors also act as a sensitivity time control STC , which suppresses lowfrequencies generated by nearby targets. Implementation of the IF frequency mitigates the flicker noise problem and allows for better selectivity due to an easier bandpass filter realization at the IF.

Microwave Circuits for 24 GHz Automotive Radar in Silicon-based Technologies

However, it requires more circuit blocks and an additional IF reference frequency. A conceptual simplified block diagram of a CW radar using heterodyne architecture is presented in Fig. The spectrum diagram of a heterodyne receiver is depicted in Fig. As can be seen, both the wanted and the image bands are down-converted to the IF frequency. Thus, the image frequency has to be suppressed before it is mixed down to the IF.

This requires a bandpass filter. For a practical filter quality factor, the IF frequency should be sufficiently high, so that the RF is far from the LO frequency. If the IF is low, image suppression at the RF becomes impossible, but signals could be processed directly at low frequencies of few megahertz and the image suppression performed at the IF [11]. For automotive radar systems in SiGe a direct down-conversion is the preferred option due to lower power consumption and complexity, whilst for CMOS a low-IF solution is preferred.

This section presents a brief overview of the current automotive radar implementations and classifies them with respect to their operating range and typical applications. Usually, several SRR sensors are equipped to fully cover the nearest surroundings of the vehicle. The primary targeted safety features are blind-spot surveillance, parking aid and ACC support [12]. Due to the low References 17 available bandwidth the range resolution is limited to 0.

Therefore, the primary targeted application for these sensors is the lane-change assistant. However, there are also systems available that offer similar functionality using a narrow-band 24 GHz radar [14]. The long-range sensors are implemented typically for ACC. This poses a challenge on circuit design, which can be relaxed by implementation of high performance technologies, based on III-V semiconductor compounds such as e. These technologies can provide transistors with very high output power, very low noise, high gain and good linearity.

However, they have a low integration level, which results in increased bill of materials BOM and module assembly costs. Implementation of circuits in cheaper silicon-based technologies offers the advantage of high integration, but at the cost of lower performance. Thus, in order to achieve sufficient performance, implementation of advanced circuit techniques is required. Until now the commercial radar sensors have used front-end chip sets realized mainly in the III-V semiconductor technologies [18], [19].

The implementations usually comprise many discrete components. Therefore, the new generation of radar sensors uses integrated circuits based on SiGe technology [20]. Future generations of radar circuit implementation would further take advantage of high integration capabilities of CMOS. Chapter 3 CMOS and Bipolar Technologies Performance capability of circuits depends to a great extent on the available semiconductor technology. Numerous parameters related to device, metallization or substrate properties circumscribe the achievable circuit characteristics at microwave frequencies and thus can be used for technology comparison.

The C11N process has been chosen due to the cost advantage compared to advanced CMOS technology nodes, whilst B7HF technology is used due to excellent high-frequency performance and high robustness. Both technologies are automotive qualified and suitable for realization of radar circuits. The structure in Fig.

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The p-well and n-well are formed in a p-type substrate without an additional intermediate epitaxial layer, since the C11N process is realized on a non-epi substrate [3]. The well can be contacted and is usually referred to as the bulk or the body. A heavily doped conductive polysilicon acts as the gate terminal. Silicide is typically used to form ohmic contacts for source, drain and gate. A thin silicon-dioxide SiO2 layer, also referred to as the gate oxide, insulates the gate from the substrate. Shallow trench isolation STI , realized using SiO2 , is implemented in order to reduce leakage between transistors and thus allow higher transistor density.

As can be seen in Fig. Thus, the bulk contacts of all NMOS transistors on one substrate are tied to the same electric potential. In this work the bulks of NMOS transistors are tied to the ground potential, whilst the bulks of PMOS transistor are connected to the source in order to reduce bulk effects. As the device dimensions continue to scale down in the modern CMOS submicrometer technologies, numerous short-channel effects, such as drain-induced barrier lowering DIBL or hot-electron effects [4] degrade the transistor performance and reliability. Therefore, the C11N technology also implements a lightly doped drain LDD implant in order to reduce the peak electric field and mitigate the hot-electron effects.

Furthermore, HALO doping is used in order to increase the average channel doping concentration and thus to increase the threshold voltage and compensate for the DIBL effect. As a result, this simplistic model provides only a very rough approximation. Additionally, solving a circuit with several transistors by means of an equivalent model including all parasitics is a very cumbersome matter.

Thus, performance evaluation at the design stage can be performed only in simulation using a considerably more complex transistor model, such as e. The circuits in this work have been simulated using enhanced BSIM 4. Careful modeling of transistor parasitics is essential for accurate simulation of microwave circuits. This is particularly important for narrow-band designs, since 3.

A BSIM model includes only the internal transistor parasitics. Thus, it has to be extended by layout-dependent external parasitics, as shown in Fig. The parasitic capacitances Cgsm ,Cgdm and Cdsm describe the capacitances between the metal interconnects leading to the transistor terminals.

The physical dimensions of the interconnects and thus the capacitance values depend on the transistor size, amount of layers used for routing, maximum allowed current density of the metal, maximum output power from the transistor and minimum allowed spacing. Values of these capacitances can reach those of intrinsic capacitances.

The gate resistance Rg depends on the layout topology and on gate contacts. CMOS transistors for high-frequency designs are usually implemented using a multifinger layout, as shown in Fig. This folded structure is advantageous for Fig. The external parasitic elements are annotated on the drawing. As may be inferred from the figure, using 22 3 CMOS and Bipolar Technologies more routing layers results in an increased metallization capacitance. Furthermore, the capacitance increases for dense routing using minimal separation between the traces. Therefore, advanced asymmetrical routing techniques for multifinger layout have been proposed in [8].

The values of the external capacitances Cgsm ,Cgdm and Cgsm are usually obtained numerically using an electromagnetic 3D field solver. The factor 12 in the denominator of the first term is valid when the gate is contacted on both sides. When the gate is contacted on one side, this factor becomes 3. The gate resistance contributes to thermal noise and degrades the high-frequency performance of a transistor.

Thus, it should be minimized for the design of microwave circuits, particularly of an LNA. The only technology-independent parameters in 3. The gate length L is usually set to the minimum allowed by technology for highest transistor speed. The first term in 3. Additionally, increasing the width W reduces the second term, but increases the first term and parasitic capacitance.

Thus, the layout can be optimized for lowest Rg. Transistors with low, regular and high threshold voltage Vt are provided. Highest performance can be achieved at 1. For stacked circuit topologies low-Vt transistors are preferred due to relaxed headroom. Several types of polysilicon, diffusion, n-well and metal resistors are provided. The lowest parasitics and thus the best high-frequency performance are achieved using polysilicon resistors. The latter has very low parasitics and a high capacitance density of 1. Additionally, it offers high linearity, low losses, good matching and reliability.

Therefore, it is used throughout this work. C technology is presented in Fig. The process is similar to the one described in [10]. It is based on a double-polysilicon self-aligned transistor concept [12] that offers low parasitic capacitances and a low extrinsic base resistance. The active area of the transistor in Fig. C base layer is grown by a selective epitaxy.

The mono-crystalline emitter contact offers a small emitter resistance. Implementation of deep trench isolation DTI reduces collector-substrate Ccs and base-collector Cbs capacitances, whilst STI is used to minimize the transistor dimensions. The drawn width of the emitter mask window in B7HF is 0. Heterojunction bipolar transistors HBT in B7HF implement a silicon germanium SiGe compound in the base in order to modify the band diagram compared to a classical bipolar homojunction transistor BJT.

The narrower band-gap of SiGe compared to Si results in a lower barrier for injection of emitter majority carriers electrons into the base, and a higher barrier for back injection of base majority carriers holes into emitter. This provides higher current gain for the same base doping level compared to a BJT. This margin is used to increase the doping at the base of an HBT in order to reduce the base resistance and to improve linearity by increasing Early voltage [13].

Additionally, Ge composition is graded across the base in order to create an accelerating electric field for minority carriers electrons and thus to achieve higher operating frequency. C of the technology. Similarly to the one described in section 3. The components Cbc ,Cbe describe the parasitic capacitance within the HBT structure, but outside the active area. Cbc describes the capacitance between the base contact and the buried layer connection to the collector, whilst Cbe describes the capacitance due to overlap of base and emitter contacts.

In this case the capacitance between the metal interconnects, described in section 3. Resistances Rb and Rc describe base and collector polysilicon and buried layer interconnect resistances, respectively. Their values depend strongly on the layout configuration. Therefore, unlike in C11N, all external parasitics are already defined in this kit, saving time and effort.

The choice of a suitable transistor layout geometry is particularly important for high frequency design in order to minimize the parasitics. In this configuration, in order to contact both sides of an active region a long bypass of base polysilicon interconnection is re- 3. In order to reduce Rb the active region can be contacted directly at the second end by an additional base contact. However, wider overlap between base and collector contacts causes higher basecollector capacitance Cbc , thus posing a trade-off between Rb and Cbc.

The larger horizontal dimension of the transistor results in a wider buried layer and thus higher collector-substrate capacitance Ccs. Furthermore, the increased distance between the active transistor area and the collector contact results in an increased Rc. Numerous further transistor configurations, such as e. Each configuration offers specific advantages and should be carefully chosen according to the application in order to optimize circuit performance.

C technology provides vertical npn and pnp transistors. However, pnp devices have a transit frequency f T of 3. The available npn transistors are classified with respect to their speed and breakdown voltage into high-voltage HV , ultra-highspeed UHS and high-speed HS devices [17]. The latter type is used in this work due to the optimal high-frequency performance. Several types of resistors are provided. It is integrated in the metallization and uses a 50 nm Al2 O2 dielectric layer. One of the main figures of merit used to quantify the transistor high-frequency performance is the maximum oscillation frequency fmax , defined under consideration of an optimum matching at input and output ports as the frequency at which the power gain becomes unity.

However, for MOS transistors fmax strongly depends on gate finger width and contact configuration, whilst it remains almost constant for different HBT sizes [18]. Thus, another common figure of merit, the transit frequency f T , defined as the frequency at which the current gain becomes unity, is used here for comparison of high-frequency performance of the devices. The maximum transit frequency of GHz, 55 GHz and 3. The optimum current densities for peak fT of 0. The PMOS transistor is much slower due to low mobility of holes.

The npn transistor offers very large margin for realization of 24 GHz applications. This is particularly advantageous for circuit performance under temperature variation, as can be observed in Fig. Additional degradation of performance parameters other than fT , occurs in CMOS due to short-channel effects. Furthermore, according to Fig. Thus, the transistors are usually operated well below the peak operation frequency. Therefore, at high temperatures the bipolar transistor offers higher performance margin. The optimum bias current for the highest transconductance gm and thus the highest gain coincides with the optimum current for the highest fT , as shown for 24 GHz in Fig.

The bipolar transistor offers a much higher transconductance of mS compared to 28 mS of NMOS transistor for these dimensions at the same bias current of 20 mA. For receiver building blocks as LNA and mixer, the transistors may be biased for the lowest minimal achievable noise figure NFmin. As can be observed in Fig. Thus, there is a tradeoff between the transistor highest operation frequency, gain and minimum achievable noise figure. The HBT offers lower minimal noise figure of 1. An additional transistor feature, particularly important for direct down-conversion mixers and voltage-controlled oscillators VCO , is the low frequency noise.

It strongly depends on bias current. For typical biasing, a bipolar transistor offers a very low flicker noise corner frequency fc of some kilohertz [20], whilst CMOS transistors have f c in the range of several megahertz. The key parameters of the presented transistors are summarized in Table 3.

C11N offers six copper layers M1-M6 and a 1. Obviously, implementation of a thick top metal results in a higher quality factor of inductors in B7HF due to a reduced ohmic series resistance. However, at higher frequencies when the skin effect is dominant, the advantage of a thick top metal is reduced. The current flows in a narrow volume close to the conductor surface defined by the skin depth [21]. Thus, higher sidewalls increase the cross-sectional area to a lesser extent compared to the case when current flows through the whole conductor volume.

Whereas, the increased distance to substrate and the higher substrate resistivity in B7HF reduce substrate losses and have stronger contribution to the quality factor improvement. Inductors having pH at 24 GHz realized as octagonal spiral coils with 2 turns in the top metal layer have been simulated in C11N and B7HF technologies. The inductors have outer radius of As shown in Fig. The maximum value of The key parameters of the available technologies are summarized in Table 3.

Schiml and et al. Pozar, Microwave Engineering, Wiley, 2nd edition, Chapter 4 Modeling Techniques Accurate modeling of components is essential for circuit design at microwave frequencies. Particular care is required during the design stage in order to consider the necessary parasitic effects. In the designs throughout this work all the passive components and the on-chip interconnects, including the pads and the transmission lines leading to the active components, are carefully simulated using the 2. However, using S-parameter models in time-domain simulations often leads to convergence and causality issues.

Therefore, in some cases lumped element equivalent circuits are used instead of the frequency based data to model passive on-chip components. This requires techniques to fit accurately frequency dependent S-parameters to an equivalent circuit in a given frequency range. Additional modeling efforts are required for active devices in CMOS.

As mentioned in section 3. Thus, it has to be extended by additional layout-dependent external parasitics describing the capacitance between the metal interconnects leading to the transistor terminals. However, obtaining values of these external capacitances is usually cumbersome and time-consuming.

Therefore, two modeling techniques are proposed in this work. The models of inductors are usually obtained in the frequency domain either through measurement or from an electromagnetic field solver simulation in form of an S-parameter file. Numerous works have been published on the developV. These approaches provide accurate results, but are usually time-consuming and require additional information about the process and inductor layout. Another option to generate an equivalent lumped element circuit is by data fitting using rational functions.

This approach provides the possibility of minimal order circuit synthesis for an arbitrary frequency dependent dataset [3]. However, the resulting circuits are less physically intuitive. An additional approach, commonly used in practice, is to perform numerical optimization by means of a computer aided design CAD tool, such as e. This is simple, but requires many iterations that might not converge. On-chip inductors exhibit physical effects that can be modeled by lumped elements as depicted in Fig. The elements of the equivalent circuit in Fig. The simplistic model in Fig. Some effects as for example eddy currents in conductive substrates, the proximity effect or distributed effects of a large inductor are not accurately described by 4.

However, it is impractical to apply analytical fitting to the advanced model. Therefore, for simplicity the data have been fitted to the 9-element spiral equivalent circuit in Fig. The proposed approach is based on Y-parameters, thus prior to applying the analysis, the S-parameter data have to be converted into Yparameters. The numerical frequency dependent admittance dataset is calculated by 4.

Depending on the required frequency range, in which the data have to be fitted, a sub-dataset, consisting of N frequency-admittance points, shall be extracted from ys. The reciprocal of the real part of admittance in 4. However, an accurate observation of the presented analytical derivation reveals that the dataset has to fulfill several conditions for this approach to be applicable.

In case that the data in the dataset do not fulfill this condition, this means that the estimation of R in the least square error sense is higher than reflected by the simple equivalent circuit model having constant component values, due to additional frequency-dependent loss mechanisms. But if there are additional losses that are not covered, this might also affect the fitting of C. The following analysis is applicable to both branches, due to their identical structure. Thus, the branches are not distinguished in this analysis for generality. In order to calculate the component values for the left branch Cox1 , Rs1 and Cs1 , the numerical dataset yp1 obtained from 4.

The ith impedance point is denoted as zi. The reciprocal of the real part of impedance in 4. Then an additional expression for Cs2 is obtained by multiplying the second equation in 4. Additional substrate loss effects, such as e. The inductor is realized as an octagonal symmetrical spiral coil with six turns on the four lowest 0. A micrograph of the inductor is presented in Fig. The test structure is designed for a low-frequency inductance of 4. The inductor S-parameters have been de-embedded using the Open-Thru approach [10]. The S-parameters have been converted to Y-parameters and separated into datasets corresponding to the series and shunt branches using 4.

The optimal values of the lumped element equivalent 4. The component values are summarized in Table 4. These data fulfill the requirements 4. Additionally, the main inductor parameters, evaluated from the measured and fitted inductor data, are compared in Fig. As can be observed, the equivalent circuit achieves an accurate fit to the inductor behavior.

The presented analysis provides simple analytical expressions for fitting frequency dependent S-parameter data of on-chip inductors in the LSE sense. This can be useful for a quick insight into the main equivalent parameters of a spiral inductor in a certain frequency range. However, due to limitations of the 9-element inductor model, the fitting procedure might provide non-physical values.

Using an advanced model, would provide robust fitting, but expressions for fitting the data in the LSE sense cannot be derived analytically. In that case a physical approach [2] or numerical optimization procedure can be used. The capacitance values are usually evaluated either by means of 3D electromagnetic field-solver simulations or through layout parasitic extraction in the design environment.

The first option is very accurate, but time-consuming. The second option is fast, but less accurate. An additional option, analyzed in this section, provides a fast and accurate capacitance estimation of a 3D structure without the use of a field solver. It is proposed to use the surface charge method SCM to estimate the transistor finger metallization capacitance numerically. Due to simplicity of the layout geometry, simple parametric meshing and fast numerical solution is possible. The surface charge method is widely used in different applications in electrostatics, such as e.

However, application of the SCM in microwave and millimeterwave engineering is uncommon, since most problems require quasi-static or fullwave numerical approaches.

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The latter are implemented in numerous commercial electromagnetic field solvers. As explained further in this section, an electrostatic approximation offered by the surface charge method is sufficiently accurate in this case, due to very small physical dimensions of the analyzed transistor finger structures compared to the wavelength. The SCM method [14] is based on the fact that in a system of conductors, when potentials are applied, the surface charges arrange themselves to make the interiors of conducting bodies field-free. By means of equivalent charge interaction, the electric potential and field distribution, induced by contributions from virtual surface point charges are derived numerically.

The values of these point charges represent the surface charge distribution, which is assumed to be uniform over the rectangular or triangular unit elements obtained by subdividing the surface of an object. For sufficiently dense discretization this procedure allows to calculate the electric 4. Several works consider the accuracy of the surface charge method [15], [16]. The capacitance value converges fast with increasing mesh density [17]. Thus, a moderately dense meshing may provide sufficiently accurate results for circuit simulations.

The theoretical background of the surface charge method is described in detail in Appendix C. The applicability of the approach has been verified by comparison of the calculated results with field solver simulations. The analyzed test structure, presented in Fig. The physical parameters of the metal and dielectric layers used in this example correspond to the C11N stack-up described in section 3.

Source and drain fingers are realized in the three lower layers M1-M3. The source and drain are connected on layers M2 and M3 on the opposite sides. The layers are connected using via arrays. The polysilicon transistor gate fingers red are connected through via arrays to metal rails in layer M1 green. For faster simulation or numerical calculation, the structure has been simplified, i.

This structure simplification approach is also common in simulations using commercial 3D field solvers in order to reduce numerical efforts. Additionally, as shown further in Fig. Thus, the main capacitance contribution is due to interaction of the faces of a single cell. Therefore, for a quick approximation only a single cell is considered and the capacitance is multiplied by the amount of cells. Rectangular meshing can be applied in this case for simplicity, since only rectangular faces are present in the structure.

Positions of equivalent point charges at the centers of the discretized cells are defined easily by triples of coordinates given in Appendix C. The discretized cell with equivalent charges replaced by dots is shown in Fig. Obviously, the equivalent capacitance of the structure varies with frequency.

However, the physical size of the transistor finger metallization is considerably smaller than the wavelength of signals in the typical IC applications. For instance, at 24 GHz the on-chip wavelength in dielectric is about 6. The dimensions of the analyzed structure are thus much smaller than of any on-chip waveguide. Therefore, distributed and dispersive effects may be neglected in this case. To confirm the presented considerations, the structure has been simulated using the full-wave field solver Ansoft HFSS.

Therefore, a static value obtained using the SCM is a valid approximation. The gate-source Cgsm , gate-drain Cgdm and drain-source Cdsm parasitic capacitances required for the extended transistor model described in Fig. References 45 Table 4. The simplicity of the rectangular problem allows straightforward meshing and simple analytical definition of equivalent charge coordinates. This can be implemented in any programming environment, as e. Excel or Matlab, allowing a quick capacitance approximation of any similar finger metallization structure with different physical dimensions.

However, if the actual layout deviates from the classical multifinger layout and additional 3D conducting objects have to be taken into account, the code has to be modified or rewritten. Furthermore, the complexity of the manual surface mesh generation and numerical efforts increase significantly with inclusion of any further bodies or problem details into the model.

Brunswig, Hochfrequenztechnik 1, chapter 4. Epperson, An introduction to numerical methods and analysis, chapter 4. Chapter 5 Measurement Techniques Accurate measurements are essential in high-frequency engineering. Depending on the functionality of the device under test DUT , different types of measurements are required. Linear characteristics of microwave circuits and devices are usually measured using a vector network analyzer VNA.

The obtained S-parameters are used to describe the main performance characteristics of the networks operating in their linear range. For example, for an LNA the small-signal S-parameters describe its gain, reverse isolation and port matching. Also for instance, the main properties of a directional coupler such as e. For non-linear characterization of microwave circuits diverse measurement instruments are required.

Many non-linear as well as linear properties can be measured using a spectrum analyzer SPA in combination with other instruments as e. For an LNA these properties are e. For a power amplifier PA these properties are e. For frequency-converting circuits, such e. For frequency generation circuits, such as e. VCO, these are output power, tuning range, output spectrum and phase noise. Obviously, several measurements can be performed using different instruments. A brief summary of measurement methods is given in Appendix D.

In all the microwave measurements there are physical components between the ports of the measurement equipment and the ports of the DUT. These components are considered to be the error networks and their impact has to be removed from measured values in order to obtain the actual DUT characteristics. In S-parameter measurements this is done by classical calibration techniques, which are typically implemented in the software package of most VNAs.

However, it is often not possible to set the measurement reference planes directly at the ports of the DUT. Thus, the impact of an error network between the calibration reference plane and the DUT has to be removed using any de-embedding technique. The magnitude of the insertion loss is then used in the equations for the cascaded connection of the DUT and the error networks in order to remove the impact of the error networks from the measured parameters and obtain the actual DUT properties.

Differential signaling becomes increasingly popular in active circuits due to its superior noise immunity and ground bounce insensitivity. However, characterization of differential circuits at microwave frequencies is a challenge. Due to cost considerations a commercial four-port or a true-differential VNA might not be easily available. Therefore, very often baluns are introduced and a differential DUT is characterized using single-ended equipment. However, there is little information in the literature on the accuracy of de-embedding using non-ideal baluns. This chapter describes several measurement considerations, developed during characterization of passive and active circuits in this work.

A detailed overview of the classical calibration methods is given in [1]. In the case that it is not possible to set the reference planes directly at the measured device, the classical de-embedding techniques such as e. Open-Short [2], Pad-Open-Short [3] or Thru [4] have to be applied to remove the impact of any error network between the reference plane and the measured device. The standard on-wafer de-embedding techniques, compared in detail in [5], can be divided into two categories. The first category consists of techniques based on equivalent lumped-element circuit models such as Short-Open, the three step or the four step methods.

These approaches assume a specific lumped-element model of interconnects. This reduces the de-embedding accuracy at higher frequencies. The second category consists of cascade-based two-port techniques, such as e. These techniques allow de-embedding to be performed without modeling of the internal structure of the error network. Thus, they are applicable up to higher frequencies and offer better accuracy than the equivalent circuit based techniques.

This section focuses on the cascade-based de-embedding techniques and proposes several extensions. This also saves the chip or board space and therefore reduces measurement costs. However, this method requires certain restricting assumptions, since the error network has several unknown terms that cannot be resolved in a single measurement. The extension introduced in [9] resolves this disadvantage at the expense of one more measurement and allows accurate characterization of asymmetrical error networks.

The networks A and B are the error networks to be de-embedded. It is assumed that the error network B represents the mirrored version of the network A, and that both networks are uncoupled. These conditions are often fulfilled in integrated circuits and precise laminate-based technologies.

An additional measurement is proposed in order to drop the requirement 5. The additional test structure could be generated by mirroring the error network and connecting it to the original error network. Due to symmetry, ports are swapped and 5. Thus, the parameters s12 and s21 of the error box are inseparable and cannot be determined unambiguously. Therefore, the reciprocity assumption 5. However, apart from the de-embedding, this approach can be useful for simplifying measurements of asymmetrical fixtures. It can be applied e.

The layout of the inductor is presented in Fig. The inductor is realized as a spiral rectangular coil with two turns on the top aluminium layer with a connection to the inner layer. The classical cascade-based Thru approach uses the test structure having the inductors connected back-to-back, as shown in Fig. The inductor is treated in this case as an error box. The proposed extended Thru version is more appropriate in this case, since on-chip inductors with undercrossing are usually asymmetrical devices that do not fulfill 5.

Therefore, an additional test structure with mirrored ports, presented in Fig. For comparison, shown in Fig. As can be seen, the additional information obtained from the second structure in Fig. In order to characterize differential devices, the mixed-mode Sparameters theory has been formulated [10] and measurement techniques using a pure-mode VNA have been developed [11]. Additionally, the multimode TRL calibration technique has been devised for characterization of multiport devices by means of multimode networks [12]. However, only few works describe the deembedding of differential devices from four-port S-parameter measurements [13].

This work proposes applying classical cascade-based two-port techniques to fourport S-parameters for de-embedding of differential networks. The four-port error networks A and B have to be de-embedded. It is assumed that the error network B represents the mirrored version of the network A and that both networks are uncoupled. The nodal S-parameter matrix Sn of a general four-port network, defined as 5. The terms sdd and scc describe differential and commonmode S-parameters respectively, whilst sdc and scd describe the mode conversion. Mode conversion can occur due to asymmetry within the differential interconnect or due to unbalanced loading [15].

If a differential structure is fully symmetrical for the signal propagation, the modes are decoupled and for a corresponding excitation pure differential mode or pure common-mode can propagate. If the structure is asymmetrical, e. In practice the differential transitions used as the error boxes are usually designed to be symmetrical with respect to the z-axis in the direction of propagation.

The asymmetry that might stem from manufacturing tolerances or from the signal path is usually negligible for frequencies up to several tens of gigahertz. As an example of a symmetrical differential error box, an on-chip transition conducting the differential signals to the active circuit area is presented in Fig. An additional example of a symmetrical transition is a test board for the characterization of a differential LNA using coaxial signaling, as presented in Fig.

One can apply these considerations and refer to Sm as the modal S-parameters of the error network A. Therefore, under the assumption of a symmetrical differential error box, the S-parameter terms describing mode conversion shall be considerably smaller than the terms corresponding to mode propagation. Thus, the modal matrix 5. The T-matrix of the thru standard is simply given by multiplication of 5. Thus, the differential and common-mode parameters remain separated and the operations can be also reduced to two-port matrices containing either mode. Obviously, upon conversion back to S-parameters the matrix maintains the same form.

Similar considerations are valid for the S-parameters of the line standard, presented in Fig. This would simply result in multiplication of the entries in 5. Therefore, under condition of negligible mode conversion on the de-embedded error networks, it is valid to treat the modes separately and apply the classical twoport TL or TRL procedures to the S-parameters of each mode separately. Obviously, the presented considerations can be further expanded to similar techniques, such as e.

The additional lines follow the same reasoning and under the assumption of a weak mode conversion the S-parameters corresponding to different modes remain separated. In practice, it is difficult to obtain the four-port S-parameters of an error-network in order to verify, whether the conditions in 5. Since the terms corresponding to the mode conversion in 5. The differential on-chip error boxes are usually designed to be symmetrical and the measured mode conversion terms commonly remain below 5.

Therefore, a practical condition equivalent to 5.

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These conditions are often fulfilled for on-chip de-embedding structures. However, if these conditions are not fulfilled, the multimode TRL [12] has to be applied for de-embedding of differential S-parameters. Now two separate cases have to be considered: Thus, in case that differential parameters of the DUT are of interest, it is sufficient to consider only the differential parameters and the matrices in 5. The matrices in 5.

Secondly, an asymmetrical on-chip differential line, simulated in the same process, describes a case of a DUT with non-negligible mode conversion. They include short, open, transmission line and thru. The DUT in this case is a 2: The chip is also manufactured in the C11N process.

The lateral spacing between the turns is 2. The cascade-based TRL [8], simplified TL [18] and the lumped-element based two-step Short-Open [2] techniques are applied for comparison. The equivalent inductance of the primary and secondary windings, de-embedded using various techniques, is presented in Fig. As can be observed, the comparison shows a very good match over a wide range of frequencies.

This is due to the fact that the physical size of the error box is much smaller compared to the wavelength and thus Short-Open is still sufficiently accurate even at 50 GHz. The larger discrepancy for the secondary side stems from the inaccuracy of TL and TRL methods using a single line standard at lower frequencies. Thus, the condition 5. In the second example, an asymmetrical differential on-chip microstrip line has been simulated using a full-wave Ansoft HFSS field-solver. The line has been realized in the top layer of the C11N layer stack-up.

Mode conversion of the DUT grows with increasing frequency. The DUT including the symmetrical differential error boxes is shown in Fig. The impact of the error boxes has been removed using 5. As can be seen, the proposed approach of de-embedding four-port DUTs using two-port methods shows accurate results also for a DUT with non-negligible mode conversion.

Thus, a common method is to measure the S-parameters of two ports, while the other two ports are terminated, as described in [19]. This method has the disadvantages of complexity, redundancy in the interpretation of measurement results and time consumption.

It requires performing a sequence of six measurements to obtain the sixteen single-ended S-parameters and to convert them into the modal representation. Another very common approach is to introduce baluns to convert between singleended and differential signals and perform the measurement using a lower cost twoport VNA or a spectrum analyzer [20].

This approach is popular due to its simplicity, but has the disadvantage of introducing additional components that cannot be easily de-embedded. Back-to-back connection of baluns is usually implemented in order to account for their impact using the widely used Insertion Loss de-embedding method. This approach is straightforward, but has a moderate accuracy and provides only the amplitude information. This section presents a generalized analytical analysis of the back-to-back baluns interconnection measurement setup and applies the results for the error estimation of the Insertion Loss technique.

Additionally, it shows analytically and in measurement that the frequency characteristics of a differential circuit measured using baluns, 64 5 Measurement Techniques might be distorted due to numerous contributions that cannot be easily accounted for. Similarly to the two-port and four-port error networks in Fig. These networks have to be characterized and their impact has to be removed from the measured results of the DUT in Fig. Furthermore, for easier interpretation of the results the modal balun S-parameters are considered.

Using these assumptions one can derive the expected S-parameters of the back-to-back interconnection in Fig. This setup is required by the widely used Insertion Loss technique in order to evaluate the balun characteristics. The Insertion Loss technique can be implemented using a two-port VNA or by means of a spectrum analyzer. Thus, under the assumption of a good port matching, high reverse isolation and negligible mode conversion, required by the Insertion Loss method, Eq.

The following analysis provides analytical expressions for the S-parameters expected to be measured for the back-to-back connection of the baluns and for the DUT measurement with baluns. The derived expressions are used in 5.

Nodal to modal S-parameter conversion for three-port devices is given in [21]. The internal ports of the multiport setup describe the differential and common-mode wave amplitudes. Following the Multiport Connection Method for evaluating circuit parameters of an arbitrarily interconnected network [22], [23], the rows and columns of the overall S-parameter matrix Sb2b are ordered so that the wave variables are separated into groups corresponding to the e external ports and i internally connected ports. For the setup in Fig. This leads naturally to de-embedding inaccuracy.

The DUT in Fig. The Multiport Connection Method is applied again to obtain the expected measured S-parameters of the setup in Fig. However, the second part of the expression shows that the common-mode gain of the amplifier is transferred through the common-mode transmission parameter of the balun and distorts the de-embedded gain. Therefore, the common-mode properties of the differential DUT also affect the de-embedding accuracy when measured using a two-port VNA and baluns.

As can be seen, the error depends both on the properties of the DUT and of the balun. In particular, the error also depends on the magnitude of the transmission S-parameter of the amplifier sDUT 21,dd that has to be de-embedded. Additionally, after developing 5. Thus, the de-embedded frequency characteristics are usually deformed and cannot be reconstructed using the Insertion Loss method. Another observation can be made without any restricting requirements on the balun parameters, but on the DUT. Firstly, two on-board test baluns based on a hybrid ring coupler, shown in Fig. Balun A has been designed to be symmetrical and balun B to be asymmetrical.

Thus, balun A offers good port isolation and matching, whilst balun B, has higher differential to common-mode conversion and degraded port matching. One branch of the balun is wider than the other one. Furthermore, the width of the trace on the 70 5 Measurement Techniques hybrid ring coupler circumference was designed to have an impedance of A direct characterization of such three-port devices in measurement is not trivial, thus the structures have been accurately simulated using HFSS. In order to obtain insight on the properties of the baluns and whether they fulfill the requirements in 5.

As can be seen, the balun B has much higher mode conversion than balun A, and can be used as an example of a balun that does not fulfill the requirements in 5. The differential matching of 5. However, poorer matching further away from the center frequency may be responsible for a higher de-embedding error at these frequencies. This test structure is used for the Insertion Loss de-embedding of the balun and corresponds to the setup in Fig.

The reference planes have been set using the four-port SOLT calibration. The back-to-back connection of the balun A has also been simulated in HFSS and compared with the measured S-parameters of the test structure in Fig. Furthermore, the simulated modal S-parameters of balun A in Fig. The comparison of the results is presented in Fig.

As can be observed, due to very careful modeling of the PCB materials and very dense meshing in HFSS, a very good match between measured and simulated results is achieved. Thus, the equations 5. The simulated S-parameters of both baluns have been used in 5. The error of the balun B reaches a maximum of 2.

The error can also become negative, which means the measured insertion loss of a balun can be estimated lower than it actually is. The LNA chip has been mounted on a board with baluns, as presented in Fig. The baluns are realized using a hybrid ring coupler centered at 24 GHz, similar to balun A in Fig. Furthermore, a chip realizing a thru standard has been bonded on an additional similar board. This allows the connection of the error 5. Obviously, a further minor inaccuracy may be introduced by non-identical error boxes caused by poor repeatability of the bondwires.

However, this inevitable inaccuracy of the described error network is minimal compared to a typical laboratory coaxial measurement setup, using for example off-the-shelf hybrid couplers. The two-port measurements have been performed on-board using GSG configuration.

Again, four-port SOLT calibration has been performed. The nodal Sparameters are converted into modal and used for comparison. The measured two-port S-parameters of the DUT s21,meas and of the back-to-back connection of the baluns s21,b2b have been used in 5. The comparison of the magnitude of the differential transmission S-parameter is presented in Fig. As can be observed, there is a gain deviation and a minor frequency shift in the de-embedded gain characteristics. Furthermore, there is a shape deformation of the frequency characteristics of the LNA. An additional erroneous inflection point is observed at 22 GHz for the curve de-embedded using the Insertion Loss method.

A maximum deviation of several decibels is observed in Fig. Martens, High-frequency characterization of electronic packaging, chapter 3. There are continuous efforts focussed on improving road traffic safety worldwide. Many driver assistance features rely on radar-based sensors. Nowadays the commercially available automotive front-end sensors are comprised of discrete components, thus making the radar modules highly-priced and suitable for integration only in premium class vehicles.

Realization of low-cost radar fro- end circuits would enable their implementation in inexpensive economy cars, c- siderably contributing to traffic safety. Cost reduction requires high-level integration of the microwave front-end c- cuitry, specifically analog and digital circuit blocks co-located on a single chip. C bipolar, make them suitable for realization of microwave sensors. Additionally, these te- nologies offer the necessary integration capability. However, the required output power and temperature stability, necessary for automotive radar sensor products, have not yet been achieved in standard digital CMOS technologies.

On the other hand, SiGe bipolar technology offers excellent high-frequency characteristics and necessary output power for automotive applications, but has lower potential for - alization of digital blocks than CMOS. Chapter 2 Radar Systems. Chapter 4 Modeling Techniques.