Analog Circuit Design: Robust Design, Sigma Delta Converters, RFID

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Our Day return guarantee still applies. Bookseller Completion Rate This reflects the percentage of orders the seller has received and filled. Minimum gate extension is 12 T at 45 nm and beyond to avoid gate-end rounding effects 46 L. In the device of Fig. In deep nanoscale technology, SA-SB average spacing for minimum-length de- vices may be tuned to achieve optimal gm values near the model default values.

In that case, it is a performance advantage for devices to be constructed with 2 finger gates. Gate-to-substrate capacitance is not substantially increased by imposing the 2-finger gate restriction. Device gate capacitance will dominate gate Ml wiring X-direction interconnect parasitic capacitance by more than an order of magnitude. Therefore the additional X-direction array width does not significantly reduce GBW. This regularity is useful in setting up global pre-layout simulation values for X and Y oxide-definition layer spacing as shown in Fig.

In the figure, upper metal layers and PMOS well patterns have been deleted for clarity. However, the WPE effect is virtually eliminated by providing uniformity in PMOS device widths and extending well patterns horizontally into adjacent cells. Figure 8 shows that in a practical HF amplifier design the use of uniform device dimensioning results in regular patterns for the trench isolation as the device pat- Fig. The spacing scheme allows regular.

This pattern regularity would not be easily achieved in the case where some devices were constructed with 2-finger gates and others were constructed with 4 or 6 fingers. It is clear that the device pattern uniformity also improves the regularity of the metal routing. Other advantages of device pitch uniformity that contribute to accuracy of precision circuits, such as C-DAC weight- ing networks, will be discussed in paragraph 7.

M adversely affect the accuracy of precise capacitor arrays [7]. Second-order quadratic lithographic errors are primarily a result of reactive-ion etch RIE loading and affect poly-poly, MIM and fringe-ca- pacitor edge pattern uniformity. Nanoscale fabrication technology has significantly improved precise capacitor edge-definition accuracy, but not significantly reduced the critical 50 0. Although it is usual practice to place 1 or 2 rows of dummy capacitors around a 2-dimensional precise capacitor array, dummy capacitors placed out to a distance up to several 10 s of microns is not area efficient.

In a 16b uncalibrated ADC used in a space-imaging application, process gradient errors are mitigated by amplifier, ca- pacitor, and switch array uniformity in 1 dimension, X [8]. Rather than adding many more rows of dummy capacitors, the CMOS devices in all amplifier and bias circuits above the C-DAC array, and comparator and logic below the array have uniform spacing and match the capacitor pitch exactly inX Uniform gradients in Fwill not substantially degrade matching.

Local and long distance interconnect parasitic capacitance Cp and resistance Rp is increasing significantly beyond the nm node as both metal and intermetal dielectric layers become thinner. In this example a clock signal is carried on M2, with shields above and Typical Cp nm vs. The figure shows the relative scale of the con- ductor width and intermetal insulator thickness. One method for mitigating these problems in the physical design is to increase the regularity of the metal patterns by achieving uniform pitch and using wider-than-minimum widths and spacings. Several IC design firms are using regular patterns for metal interconnect at the 45 nm node.

A representative sample obtained by reverse engineering an Intel 45 nm logic chip [9] is shown in Fig. Note that pattern fidelity is improved by arranging metal patterns primarily in one direction on each layer in this case M2 and M3. Lewyn 9 Summary and Conclusions In the nanoscale era of analog CMOS design, an understanding of the factors affect- ing physical design is becoming increasingly important. The level of understanding will be reflected in the quality of the initial circuit design.

Device physical design uniformity is helpful to assure both lithographic pattern fidelity and simplify the specification of pre-layout STI, WPE, and oxide- definition-spacing simulation parameters. Induced stress from adjacent device pat- terns and local wiring are becoming dominant physical design considerations. At the 45 nm node and beyond, there must be close collaboration between circuit and physical design activities in order to assure a manufacturable IC and avoid long rework cycles following post-layout design verification.

Where high performance analog circuits are a significant fraction of the SOC, leading IC design companies are requiring analog circuit designers to work more closely with the physical design team, or in some cases, perform the physical circuit layout. The historical separation of circuit and physical design may also be improved by physical designers assum- ing more responsibility in the circuit design, simulation and verification.

The problems facing analog circuit design in nanoscale technology nodes with se- vere voltage restrictions and physical design constraints appear formidable. However, they can be mitigated and overcome with the same kind of dedication and innovation demonstrated by Si foundry process development engineers to keep pace with Moore's law in advancing process technology generations every 2 years.

Implementing regular device patterns and other physical design strategies at the beginning of a project may require some additional design time. However, these strategies have been implemented on previously-successful IC design projects. The extra planning and implementation time required is small compared to the re-design time required in projects where many physical design defects are found late in the pre-tapeout verification cycle.

Electron Devices 55 1 , M.

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Templeton, When IC yield missed the target, who is at fault? IEEE 97 10 , Y. Electron Devices 53 11 , C. Juang, Impact of STI effect on flicker noise in 0. Dunkley, Systematic capacitance matching errors and corrective layout procedures. Solid-State Circuits 29 5 , 8. Higher segments will require further developments in storage systems thus being expected to come on the market late where commercial delivery vans, trucks, minibuses and urban buses together with electric bicycles and scooters have already gained significant market shares: The nanoelectronics technologies and power electronics devices, circuits and modules will address the needs of x, A and B segments.

This can be achieved by smart integrated power electronic modules by ap- plying high temperature power electronics and ultra high power density mechatronics. The architecture of the EVs and HEVs aggregate devices, power modules, pro- cessing units, embedded systems, algorithms, mechatronics modules and mechani- cal parts in five main functional domains [3]: The development of power electronics technologies, devices, circuits and modules for these functional domains can be clustered in four design areas: Box Blindern, Oslo, Norway H.

These solutions are used to process sensor signals, drive actuators and enable further reduction of energy consumption, driver assistance systems and comfort functions. The need for power electronics modules and mixed signal smart power IC's that combine digital and analog signal processing and power switches is in- creasing. Battery monitoring systems for the electrical vehicles are designed using the smart power technology. For example electro thermal simulation provides solutions for determin- ing the temperature of each component on the circuit for all operating conditions allowing to verify circuit performance and to guarantee a lifetime well beyond specification.

The reliability of the semiconductor devices used in EVs and HEVs automo- tive applications is a very important issue, as these devices and modules have to operate under harsh environmental conditions such as high temperatures, humidity and vibrations. A significant increase in the system reliability can be achieved by monolithic integration of different functions on the same chip, where hybrid solu- tions typically suffer from reduced reliability owing to many interconnects, plugs and complex mounting procedures.

In this context the power electronics contribute to energy saving and improved efficiency in several aspects: The key for market accep- tance and market penetration is costs requiring a mechatronic integration of power electronics in the application system, together with sensors and informa- tion and communication technologies.

The new developments in automotive industry on EVs and HEVs have specific requirements to power semiconductors. To reach smaller form-factor requirements, temperature and power management are key issues for power and control electronics in vehicles. To minimise the cooling demand, it would be necessary to increase the maxi- mum allowable junction temperature.

This increase can be fully exploited as the conduction losses are almost independent of the temperature and the switching losses are 56 0. The motivation to develop high temperature smart power products is presented Table 1 [4] and 2 [1], which shows a summary of the requirements for high tem- perature electronics. In this way the packaging becomes cheaper, the power module becomes easier to build, and the chip area of the semiconductor device can be made smaller.

Smart power applications are spread over a broad voltage range. Similar require- ments for high temperature applications are found in the power electronics of dif- ferent transportation systems such as cars, airplanes, satellites, and even railway systems. The market for high temperature high voltage devices spans from low voltage automotive applications up to 60 V to grid connection V AC up to electronics for power traction V and over.

The technological trends for power devices are pre- sented in Fig. The trends in the IGBT module on increasing their power capacity greatly help to contribute to system downsizing. The optimum combination of the new silicon and new package technologies results the most economical solution for each module ratings. SiC unipolar devices MOSFETs have a potential to replace bipolar IGBT de- vices in various application fields, including automotive power electronics and very high voltage systems; however several critical issues remain, like improving wafer size and quality, solving device processing hurdles.

Similar stresses may occur for other auxiliary motor drives or DC-DC conversion applications. The power semiconductors and packages must show very high reliability: The reliability assurance requires the evaluation of parameters from technology, system and stress profde in order to generate the stress on the specified electric vehi- cle module and system in operation. Based on the system description and the system simulation thermal, corners, etc.

The concept is presented in Fig. The important input parameters are the current paths required by the load. In the electronics modules the reliability risks can be identified by using the failure mode cause and effect analysis into four areas: The failures are evaluated based on following criteria: In order to determine the physics of failures for the electronics for EVs and HEs different type of test are required.

Accelerated tests must be developed and verified for each specific fault mechanism. For example, a highly accelerated test is applied to bond wires. The fault mechanism can have two elements, the different coeffi- cients of thermal expansion of the bond wires compared with the metallization on the silicon chip, and the natural oxide layer formed on the solder.

System dependability, defined as the quality of a delivered service such that reli- ance can justifiably be placed on this service, is evaluated by measuring the follow- ing magnitudes: Robust Design for High Temperature and High Voltage Applications 6 1 For the electronics modules used in EVs and HEVs the failure is considered the event that occurs when the delivered service of the electronic system deviates from the specified mission.

In this case the error is the part of the system state which is liable to lead to failure and the fault is the phenomenological cause of the error. The most frequently used reliability measure for semiconductor devices is the failure rate X. The failure rate is obtained by dividing the number of failures observed, by the product of the number of devices observed and the number of hours operated, usually expressed as the percent of failures per thousand hours, or failures per bil- lion device hours FITS.

The semiconductor industry uses highly accelerated testing procedures to as- sess the reliability of semiconductors. During accelerated tests, combinations of stresses over the normal values, are used to produce, in a short period, the same fail- ure mechanisms as would be observed during normal use conditions. Temperature, relative humidity, and voltage are the most commonly used stresses used during accelerated testing. For instance the devices are tested near their maximum junction temperatures and failures are analyzed to verify that they are of a type that is accel- erated by temperature.

This gives an estimation of most probable failures, but does not give any information on when the failure will occur. Afterwards ad-hoc tests over the most probable failure mechanisms, together with combination models, are used to estimate the failure rate X. In order to design a dependable system a combination of the following tech- niques are considered for the electronics modules: A combination of these techniques must be used to obtain a dependable system.

In the electronic modules for EVs and HEVs the complexity of the systems re- quires a system level approach in order to cope with all these aspects and to achieve the best compromise between reliability and costs; moreover, it is only a combined utilization of different techniques that can lead to a dependable system. In this con- text it is necessary to decrease detection and correction costs, and move the focus to failures instead of faults.

In the case of electronics modules for EVs and HEVs it is necessary to use a methodology including simulation software reliability analysis, use of fault injec- tion at different abstraction level and selection of a mix of hardware and software protecting techniques and thus creating a fault robust approach for high temperature and high voltage applications, where robustness is considered the ability of a mod- ule to continue to function despite the existence of faults in its component subsys- 62 O.

The goal of robust design for electronics modules for EVs and HEVs is to cre- ate circuits whose characteristics remain within the called design requirements re- gardless of possible semiconductor manufacturing process variations and changing operating conditions. A circuit characteristic is any real quantity that can be measured on a circuit.

The operating conditions i. The manu- facturing process variations which can occur during IC fabrication are provided by the circuit foundry. We focus on those design problems where these variations are provided in the form of corner models of circuit elements. For a CMOS process usu- ally the following corners are provided: Corner models can also be provided for resistors, capacitors, IGBTs, etc.

In order to obtain a robust circuit an additional step of design centering is re- quired by using statistical or deterministic design centring techniques. Robust design used by IC designers relies on the assumption that circuit char- acteristics have their extreme values at the extremes of operating conditions and process variations. A circuit is checked to be robust by simulating it against the combinations of extreme operating conditions and process variations.

This assump- tion is valid only if circuit characteristics are monotonic functions on the intervals enclosing operating conditions and model parameters of corner models. This is especially important for very short pulses up to a few hundredths of nanoseconds like in ESD events. The hot carrier effect plays on a time scale of seconds to years. Pulse times are typically in the sec. They are placed in the circuit in between the accumulators and the AC motor.

The flow of energy is controlled by commanding the power devices to switch on and off repeatedly. This condition is a function of the simultaneous voltage Robust Design for High Temperature and High Voltage Applications 63 imposed across the device and current flow through it. These transients may be described as turn ON and turn OFF, and each of these transients may have a charac- teristic stress on the power semiconductor device. The SOA of a device is an absolute rating and the failure mode when exceeding it, is a catastrophic failure of the device.

To get highest reliabilities, the SOA of a device is defined in such a way to allow the device to handle the worst case transient current simultaneously with the highest input voltage without damage. Thermal simulation has to consider the circuit in operation with the heat flowing away from the heat source and increasing temperature of the neighbouring devices; this simulation is iterative since the transistor currents are temperature dependent.

In this simulation, all aspects have to be taken into account: Currents in large drivers might not be homogeneous and the simulation needs to consider the layout of the switch, including all the resistors. The thermal resistance of the package is another key parameter. The Heatwave package is commonly used for dynamic electro-thermal simula- tions: It flags to the designer the local hot spots and the associated risks for thermal run-away. It must also be noted that temperature gradi- ents over the die could lead to other artefacts such as mismatch of transistor currents and parameter shifts.

It is well known that these risks are strongly temperature dependent typically exponential. A model of the device ageing parameter shifts as a function of applied voltage, current and temperature can be generated based on extensive device stressing ex- periments. Possible ageing and failure modes for the silicon devices are hot carrier instability of transistors, time dependent dielectric breakdown of gate oxides and electro-migration of metal interconnections on chip [5]. Failures related to the package are even more difficult to model since they not only depend on electrical and thermal stress but also on mechanical stress in the 64 O.

Modelling requires the characterization of the package moulding com- pound during thermal cycling. Basic models are typically implemented in quick and dirty reliability calculators running in EXCEL or MathCAD environments to be used by the designers for a first dimensioning design. Each calculator typical considers one reliability aspect at a time e.

Advanced reliability simulators considering several ageing aspects together are used as a final design check over a block or a complete circuit. The outcome of the reliability simulator can be a maximum parameter shift for a certain transistor at the end of life or flags that indicate that certain devices or blocks poses some risk and should be further analysed. However both quick and dirty calculators and reliability simulators can handle complicated temperature profiles e.

The hybrid modules distribute signal and power, dissipate heat, protect the devices enclosed, and serve as the basic power electronics building block.

Power module design has to address the inherent mechanical stresses after bond- ing of large silicon chips having low coefficient of thermal expansion CTE with other materials having higher CTE. The power module technology relies on the use of aluminium wire bonds, direct bond copper ceramic substrates, and copper base plates. The thin aluminium wire bonds suffer from high parasitic impedance, fatigue-induced lift-off failures, and inability to remove heat. The DBC ceramic substrate A1 2 3 or more expensive A1N provides electrical isolation but inadvertently increases the package thermal resistance.

The thick Cu base plate serves as a heat spreader but considerably increases the weight, size, and thermal resistance of the power module. To connect the top side of the chips, wire bonding is usually employed. Multiple substrates are con- nected to a base plate by use of soft-solder joints. Changing the maximum allowable junction temperature of the power semicon- ductor will directly change the thermal stress on the interconnection of the chip surface.

A typical wear out effect at the chip surface is the wire bond lift off. To test this interconnection, power cycling tests are performed. The number of cycles that a device survives is related to the temperature swing, the maximum temperature and the slopes. Robust Design for High Temperature and High Voltage Applications 65 Over the lifetime of direct bond copper DCB modules, the layers are prone to recurring mechanical stress, due to the ongoing thermal cycles. Caused by the current flow in the semiconductor and the resulting heat-up, the materials used, such as copper, ceramics, silicon and aluminium expand with their different coefficients of expansion.

This combination of materials is mainly suitable for EV systems and some full hybrid systems. When designing the power semiconductor module, particular consideration needs to be given to the load profile during the lifetime of the EV and HEV. On that basis, thermal interface material and the metallization poses the major role to heat removal in the system. Carbon nanotubes CNTs are allotropes of carbon having novel properties, for example unique electrical and thermal properties that make them useful in various applications such as nanotechnology, electronics, op- tics and other fields of materials science.

The electric current carrying capability of Single-wall carbon nanotubes A cm -2 SWCNTs is estimated to be A cm -2 while copper wires burn out at about A cm" 2. More over, the thermal conductiv- ity of these nanotubes is 3, Wm" 1 K" 1 compared to Wm" 1 K" 1 for copper. Composite materials made of metal and CNT are expected to provide unique electrical and thermal interface in the condition of high voltage and in high ambient temperature. It has been characterized using X-ray diffracting and carbon analysis to confirm the metal and the amount of carbon percentage.

Surface morphology has been examined using scanning electron microscopy SEM and electrical resistivity is measured using standard four point probe meth- od, where electrical resistivity found to be varied with the deposition condition of the composites Fig. In power devices operating at high ambient 66 O. There- fore a global thermal management solution optimised at all levels device, module and system is required to achieve a lower junction temperature.

Analog Circuit Design - Robust Design, Sigma Delta Converters, RFID

At device level, the thermal management solution will provide a good thermal path for heat spreading and heat transport away from the junction. High conductivity materials and thermal interfaces are therefore essential. Hence, at module and mostly at device level, heat conduction is the most im- portant factor to optimise. Finally, at system level, the heat which had been carried away from the heat sources must be dissipated to the surrounding ambient by con- vection and sometimes radiation.

However, an overall optimised thermal management will only be achieved if all levels are considered jointly. Computational Fluid Dynamics CFD solvers are an essential tool to support the design and optimisation of thermal management at all levels, as they can accurately predict the conduction, convection and radiation behaviour.

New tools such as thermal electric simulators and reliability simulator assist the designer to achieve these goals for high robustness. Robust Design for High Temperature and High Voltage Applications 67 Thermal electric simulators are fully deployed by semiconductor companies for the design of automotive smart power circuits.

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Reliability calculators are in use for many reliability aspects while the use of the novel multi-physic reliability simula- tors is in an early stage. Thermal simulations can be used to adjust the thermal characteristics of the de- vice to the worst case operating conditions and the maximum temperature allowed. Planar and stacked configura- tions will be used for the integrated power modules and as the requirements for miniaturisation are becoming critical, the stacked substrates approach may become preferred.

The authors would also like to convey thanks to the Public Authorities and European Commission for providing the financial support. Energy, Jan J.

Korec, Silicon-on-insulator technology for high-temperature, smart-power applications. The engineering community involved in each of these disciplines has developed over time its specific set of solutions to ensure system reliability. Nevertheless, the need for extensive irradiation campaigns in view of selecting first, then assuring reproducible radiation response of the components increases the cost and required testing resources.

On the other hand, the development or purchase of dedicated "radiation-tolerant" components eases qualification and procurement and ensures the required level of reliability, but is typically more expensive. This cost is in part determined by the need for using a dedicated manufacturing process most often CMOS qualified against radiation effects. The low volume of this market, together with its strict quality as- surance requirements, make the business profitable for a small number of "niche" foundries only if silicon wafers can be sold at large prices for a relatively long time.

Processes are therefore not phased out as quickly as in the commercial marketplace, and new developments take more time. As a result, they are typically lagging two generations or more behind commercial-grade products.

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An alternative approach, increasingly popular in the last decade, is based on the use of commercial standard CMOS technologies. This allows circuit designers to using state-of-the-art processes to design ICs, while at the same time delivering radiation- tolerant components. In doing so, designers must be aware of the radiation effects F.

Faccio against which circuits have to be protected. SEEs are instead due to the prompt charge deposition originating from a single ionizing particle in the semiconductor, and as such have a stochastic nature: Modern LDMOS are actually degrading their performance only at high particle fluence, much larger than the typical radiation environment in space applications but not larger than the one found in the latest generation of HEP experiments, or in civilian nuclear applications.

Ionizing radiation creates electron-hole pairs in the oxide, with consequent trapping of holes or activation of defect states at the interface between the oxide and silicon interface states. Depending on the posi- tion, function and nature of the oxide where these phenomena happen, the conse- quences on the circuit can be different. In the gate oxide, the electric characteristics of the transistor might be affected threshold voltage, mobility, noise. Trapped charge can be de-trapped or "annealed" by thermal excitation at a rate dependent on the energy of the traps. The points at ran and below are only indicative, since the V h shift is so small that a large statistical study should be done to determine the real value.

With the sam- ple size available, the error bars are comparable to the measured values mV 1. C U4 i 10 tox A 2 t ox nm Research work in the s already revealed how the density of trapped holes and interface states both depend on the oxide thickness: This has been confirmed since by several sources on commercial-grade gate oxides in advanced CMOS. Already around 5 nm, the shift is practically negligible for most applications: At 2 nm, gate oxide thick- ness typical of the nm nodes, the radiation-induced shift is negligible even at doses of the order of Mrad.

Additional evidence of the robustness of the gate oxide emerges from noise measurements in these technology nodes: Unfortunately, no data is available on commercial high-K dielectrics re- placing nitrated oxides as gate dielectrics in very advanced CMOS as from 45 nm. Experimental data is not very useful in this case, since it only concerns laboratory dielectrics which might not be even similar to what actually used industrially. While the thickness of the gate oxide decreases with down-scaling, the STI ox- ide thickness remains very comparable. Hole trapping in this oxide — leading to leakage currents — is therefore still a relevant failure mechanism.

In particular, the leakage problem is worst at the edges of NMOS transistors where the polysilicon gate extends beyond the transistor channel and overlaps the lateral STI. When the NMOS transistor is turned on, an electric field is also present across the STI at the edge of the transistor, enhancing hole trapping.

The accumulation of trapped holes in the STI reinforces the electric field in this region, and eventually inversion at the transistor edges occurs even if the main transistor is turned off, and leakage current can flow in the inversion layer [4]. Contrary to the gate oxide case, where for the same thickness the radiation re- sponse of samples from different manufacturers is very comparable Fig.

The peaking of the leakage at doses of Mrad has been studied in detail and attributed to the compensating contribution of negative charge trapped in defect states at the interface between the STI oxide and the silicon that compensate for the holes trapped in the STI oxide [6]. More recent data in 90 nm, shown in Fig. It is interesting to note that the source-drain leakage current evolution is comparable for manufacturers A and B in and 90 nm. Before exposure to radiation, the threshold voltage of these transistors is typically well above 10 V, and no current flows in the device when the gate and drain are biased at the maximum Vdd up to 3.

E- 2 1. However, hole trapping in the STI reduces the threshold voltage until current flows in the device also when no bias is applied to the gate — the leakage current in the example reaches 1 jlA. The comparison of available data in different tech- nology nodes reveals how this effect gets milder in and 90 nm with respect to older processes: However, these measurements on a small sample of technologies can not be generally extrapolated: If the hit perturbs the logic state of a memory or register, causing a switch to the "wrong" state, the event is called Single Event Upset SEU.

Its consequences might be unobservable if the stored bit is actually not used, or cause the whole IC to hang in a wrong state requiring a reset — in which case the event is called Func- tional Interrupt SEFI. Because of the increased speed of new technologies the gate delay is shorter than the duration of the perturbation introduced by the strike of the ionizing particle , hits in the combinatorial logic can now propagate through a long series of gates.

These glitches can reach the input of a register where, if they hazardously happen to be synchronous to the proper clock transition, they can be latched [7] giving origin to a "Digital" Single Event Transient DSET. Since the wrong value can only be latched during a clock transition, the DSET error rate de- pends linearly on the clock frequency.

These are especially relevant at the input of amplifiers, in high im- pedance nodes, and in the presence of precise small currents. In some cases, SEEs can lead to permanent failure. Sensitivity to SEU clearly depends on the ratio between the charge stored in a node during normal operation versus the one collected from a particle hit.

Since the former decreases with down-scaling both node capacitance and Vdd decrease , a larger sensitivity to SEU was generally expected for modern technologies. This forecast actually did not materialize. Recently published data, comparing per-bit sensitivity of memory cells in five con- secutive generations from the same manufacturer, clearly show a fold decrease of the error rate when going from to 65 nm [9] actually, comparison of pre- dicted error rates for the two cells in a geostationary orbit indicates a factor of 60 difference.

This highlights how node capacitance and voltage supply alone are not a sufficient indicator: The reason why most semiconductor industries, which do not target the niche market of radiation tolerant components, have made the effort to carefully char- acterize SEU sensitivity of their products lies in the growing concern for large neutron- induced error rates in terrestrial large-scale applications [8].

Radiation is present at ground from natural sources — mainly from cosmic rays — and this radia- tion background can significantly contribute to increase the Failure In Time FIT of the components, especially for large memory banks. In particular, thermal neutrons have been shown to largely dominate the error rate in some components. When this mechanism was identified, semiconductor manufacturers replaced BPSG with an alternative material, effectively reducing the FIT of their components. Due to the presence of multiple adjacent n- and p-doped regions in CMOS technologies, parasitic npnp or pnpn structures called thyristors can be found all over the ICs.

Such structures can be turned on by the flow of cur- rent induced by an ionizing particle's hit. This can lead to a latched low-impedance path between Vdd and ground which, if not promptly interrupted, can permanently damage the device. In the last 15 years, the introduction of STI and retrograde wells together with the steady reduction of the voltage supply has been very beneficial in reducing the general sensitivity of ICs to SEL [11]. However, this alone does not guarantee immunity from latch-up, since SEL is extremely design dependent and very sensitive components can still be found.

This destructive event can occur when the transistor is turned off and has to stand the full rated Vds: These transistors are frequently offered in "high-voltage" versions of CMOS technologies, added to the 76 F. Faccio standard low-voltage transistors for mixed-signal applications, and are frequently used for RF amplifiers or DCDC converters or more generally in power manage- ment ICs.

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